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dinesh koli
dinesh koli
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Cited by
Cited by
Year
FinFET performance advantage at 22nm: An AC perspective
M Guillorn, J Chang, A Bryant, N Fuller, O Dokumaci, X Wang, J Newbury, ...
2008 Symposium on VLSI Technology, 12-13, 2008
1232008
A 7nm CMOS technology platform for mobile and high performance compute application
S Narasimha, B Jagannathan, A Ogino, D Jaeger, B Greene, C Sheraw, ...
2017 IEEE International Electron Devices Meeting (IEDM), 29.5. 1-29.5. 4, 2017
642017
Study of the cross contamination effect on post CMP in situ cleaning process
HJ Kim, G Bohra, H Yang, SG Ahn, L Qin, D Koli
Microelectronic engineering 136, 36-41, 2015
522015
Cobalt CMP development for 7nm logic device
C Wu, JH Han, X Shi, DR Koli, D Penigalapati
ECS Transactions 77 (5), 93, 2017
372017
Formation of cobalt-BTA complexes and their removal from various surfaces relevant to cobalt interconnect applications
J Seo, SH Vegi, CK Ranaweera, NK Baradanahalli, JH Han, D Koli, ...
ECS Journal of Solid State Science and Technology 8 (5), P3009, 2018
362018
High performance bulk planar 20nm CMOS technology for low power mobile applications
H Shang, S Jain, E Josse, E Alptekin, MH Nam, SW Kim, KH Cho, I Kim, ...
2012 Symposium on VLSI Technology (VLSIT), 129-130, 2012
302012
Implantless dopant segregation for silicide contacts
C Cabral Jr, JM Cotte, DR Koli, LL Kosbar, M Krishnan, C Lavoie, ...
US Patent 8,889,537, 2014
152014
Effects of pad temperature on the chemical mechanical polishing of tungsten
HJ Kim, SG Ahn, L Qin, D Koli, V Govindarajulu, Y Moon
ECS Journal of Solid State Science and Technology 3 (10), P310, 2014
142014
Chemical mechanical planarization processes for fabrication of FinFET devices
JB Chang, L Charns, JE Cummings, MA Guillorn, LJ Hupka, DR Koli, ...
US Patent 8,513,127, 2013
142013
Advanced structure for self-aligned contact and method for producing the same
H Huang, D Koli, Y Zhou, X Shi, CC Chang, TF Chao
US Patent 10,211,103, 2019
102019
20nm CMP model calibration with optmized metrology data and CMP model applications
U Katakamsetty, D Koli, C Hui, R Ghulghazaryan, B Aytuna, J Wilson
SPIE Proceedings 9427, 2015
102015
Common fill of gate and source and drain contacts
D Konduparthi, D Koli
US Patent 9,136,131, 2015
92015
Planarization scheme for finfet gate height uniformity control
S Muralidharan, Z Hu, Q Zhang, JH Han, D Koli, Z Chen
US Patent App. 14/153,120, 2015
92015
Chemical mechanical planarization with overburden mask
L Charns, JM Cotte, JE Cummings, LJ Hupka, DR Koli, T Konno, ...
US Patent 8,524,606, 2013
82013
Challenges in chemical mechanical planarization defects of 7nm device and its improvement opportunities
JC Yang, D Penigalapati, TF Chao, WY Lu, D Koli
2017 China Semiconductor Technology International Conference (CSTIC), 1-3, 2017
72017
CMP challenges for advanced technology nodes
JH Zhang, H Huang, AM Greene, R Xie, SC Seo, P Montanini, WT Tseng, ...
MRS Advances 2 (44), 2361-2372, 2017
72017
New CMP processes development and challenges for 7nm and beyond
H Huang, D Koli, JH Zhang, S Tsai, T Chao, Y Lu, HJ Kim, Q Fang, W Lu
2018 China Semiconductor Technology International Conference (CSTIC), 1-5, 2018
62018
Metal Flake Defect and Its Formation Mechanism during Replacement Metal Gate CMP Process
DK Hong Jin Kim, Venugopal Govindarajulu, Girish Bohra, Huey-Ming Wang
ECS J. Solid State Sci. Technol. 2016 volume 5, issue 10, P637-P640 5 (10 …, 2016
6*2016
Effect of reactive ion etch on the polishing selectivity during silicon nitride chemical mechanical polishing for sub-10 nm logic device
J Han, X Shi, C Wu, D Koli, HJ Kim
ECS Journal of Solid State Science and Technology 6 (4), P101, 2017
52017
A Study on Selectivity during SiN Chemical Mechanical Polishing for Sub-10nm Logic Device
JH Han, X Shi, C Wu, D Koli
International Conference on Planarization/CMP Technology (ICPT 2016), 17-19, 2016
52016
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