Donggyu Kim
Cited by
Cited by
The rocket chip generator
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016
Firesim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud
S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, N Pemberton, ...
Proceedings of the 45th Annual International Symposium on Computer …, 2018
Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
A Izraelevitz, J Koenig, P Li, R Lin, A Wang, A Magyar, D Kim, C Schmidt, ...
Proceedings of the 36th International Conference on Computer-Aided Design …, 2017
RFUZZ: coverage-directed fuzz testing of RTL on FPGAs
K Laeufer, J Koenig, D Kim, J Bachrach, K Sen
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
Strober: fast and accurate sample-based energy simulation for arbitrary RTL
D Kim, A Izraelevitz, C Celio, H Kim, B Zimmer, Y Lee, J Bachrach, ...
Proceedings of the 43rd International Symposium on Computer Architecture …, 2016
Evaluation of RISC-V RTL with FPGA-Accelerated Simulation
D Kim, C Celio, D Biancolin, J Bachrach, K Asanovic
1st Workshop on Computer Architecture Research with RISC-V (CARRV '17), 2017
Fased: Fpga-accelerated simulation and evaluation of dram
D Biancolin, S Karandikar, D Kim, J Koenig, A Waterman, J Bachrach, ...
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection
D Kim, J Zhao, J Bachrach, K Asanović
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles
D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanović
2018 28th International Conference on Field Programmable Logic and …, 2018
FPGA-Accelerated Evaluation and Verification of RTL Designs
D Kim
UC Berkeley, 2019
Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud
D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanovic
2nd Workshop on Computer Architecture Research with RISC-V (CARRV '18), 2018
RTL bug localization through LTL specification mining (WIP)
V Iyer, D Kim, B Nikolic, SA Seshia
Proceedings of the 17th ACM-IEEE International Conference on Formal Methods …, 2019
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