| The effective drive current in CMOS inverters MH Na, EJ Nowak, W Haensch, J Cai Digest. International Electron Devices Meeting,, 121-124, 2002 | 273 | 2002 |
| High-/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length MH Khater, Z Zhang, J Cai, C Lavoie, C D'Emic, Q Yang, B Yang, ... IEEE Electron Device Letters 31 (4), 275-277, 2010 | 205 | 2010 |
| Low power circuit design based on heterojunction tunneling transistors (HETTs) D Kim, Y Lee, J Cai, I Lauer, L Chang, SJ Koester, D Sylvester, D Blaauw Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009 | 160 | 2009 |
| High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization CH Lin, B Greene, S Narasimha, J Cai, A Bryant, C Radens, V Narayanan, ... 2014 IEEE International Electron Devices Meeting, 3.8. 1-3.8. 3, 2014 | 159 | 2014 |
| Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method J Cai, A Majumdar, TH Ning, Z Ren US Patent 8,329,564, 2012 | 156 | 2012 |
| High performance low power bulk FET device and method of manufacture J Cai, T Furukawa, RR Robison US Patent 8,361,872, 2013 | 128 | 2013 |
| Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors J Cai, CT Sah Journal of Applied Physics 89 (4), 2272-2285, 2001 | 117 | 2001 |
| A perspective on today’s scaling challenges and possible future directions RH Dennard, J Cai, A Kumar Solid-State Electronics 51 (4), 518-525, 2007 | 105* | 2007 |
| A 3-transistor DRAM cell with gated diode for enhanced speed and retention time W Luk, J Cai, R Dennard, M Immediato, S Kosonocky 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 184-185, 2006 | 88 | 2006 |
| Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond Q Liu, A Yagishita, N Loubet, A Khakifirooz, P Kulkarni, T Yamamoto, ... 2010 Symposium on VLSI Technology, 61-62, 2010 | 86 | 2010 |
| Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors J Cai, J Chang, L Chang, BL Ji, SJ Koester, A Majumdar US Patent 7,985,633, 2011 | 85 | 2011 |
| CMOS EPROM and EEPROM devices and programmable CMOS inverters J Cai, TH Ning, JM Safran US Patent 7,700,993, 2010 | 82 | 2010 |
| ETSOI CMOS with back gates J Cai, RH Dennard, A Khakifirooz US Patent 8,415,743, 2013 | 81 | 2013 |
| Impact of back bias on ultra-thin body and BOX (UTBB) devices Q Liu, F Monsieur, A Kumar, T Yamamoto, A Yagishita, P Kulkarni, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 160-161, 2011 | 69 | 2011 |
| Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate J Cai, H Chen, Q Ouyang, T Ning 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE …, 2003 | 62 | 2003 |
| On the performance and scaling of symmetric lateral bipolar transistors on SOI TH Ning, J Cai IEEE Journal of the Electron Devices Society 1 (1), 21-27, 2013 | 55 | 2013 |
| Monitoring interface traps by DCIV method J Cai, CT Sah IEEE Electron Device Letters 20 (1), 60-63, 1999 | 55 | 1999 |
| Interfacial electronic traps in surface controlled transistors J Cai, CT Sah IEEE Transactions on Electron Devices 47 (3), 576-583, 2000 | 46 | 2000 |
| ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2SRAM cell K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, B Haran, A Kumar, T Adam, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 128-129, 2011 | 45 | 2011 |
| Complementary thin-base symmetric lateral bipolar transistors on SOI J Cai, TH Ning, C D'Emic, KK Chan, WE Haensch, JB Yau, DG Park 2011 International Electron Devices Meeting, 16.3. 1-16.3. 4, 2011 | 44 | 2011 |
