Deepak Vinayak Kadetotad
Deepak Vinayak Kadetotad
Starkey Hearing Technologies
Verified email at asu.edu - Homepage
Title
Cited by
Cited by
Year
Face recognition using transform domain feature extraction and PSO-based feature selection
NLA Krisshna, VK Deepak, K Manikantan, S Ramachandran
Applied Soft Computing 22, 141-161, 2014
892014
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip
PY Chen, D Kadetotad, Z Xu, A Mohanty, B Lin, J Ye, S Vrudhula, J Seo, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 854-859, 2015
782015
Parallel architecture with resistive crosspoint array for dictionary learning acceleration
D Kadetotad, Z Xu, A Mohanty, PY Chen, B Lin, J Ye, S Vrudhula, S Yu, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015
602015
A 1.06- W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring
S Yin, M Kim, D Kadetotad, Y Liu, C Bae, SJ Kim, Y Cao, J Seo
IEEE Journal of Solid-State Circuits 54 (8), 2316-2326, 2019
362019
Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications
D Kadetotad, S Arunachalam, C Chakrabarti, J Seo
Proceedings of the 35th International Conference on Computer-Aided Design, 1-8, 2016
352016
On-chip sparse learning acceleration with CMOS and resistive synaptic devices
J Seo, B Lin, M Kim, PY Chen, D Kadetotad, Z Xu, A Mohanty, S Vrudhula, ...
IEEE Transactions on Nanotechnology 14 (6), 969-979, 2015
232015
Parallel programming of resistive cross-point array for synaptic plasticity
Z Xu, A Mohanty, PY Chen, D Kadetotad, B Lin, J Ye, S Vrudhula, S Yu, ...
Procedia Computer Science 41, 126-133, 2014
202014
ECG authentication neural network hardware design with collective optimization of low precision and structured compression
SK Cherupally, G Srivastava, S Yin, D Kadetotad, C Bae, SJ Kim, J Seo
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
13*2019
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning
D Kadetotad, Z Xu, A Mohanty, PY Chen, B Lin, J Ye, S Vrudhula, S Yu, ...
2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings …, 2014
132014
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition
K Chang, D Kadetotad, Y Cao, J Seo, SK Lim
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
112017
Low-power neuromorphic speech recognition engine with coarse-grain sparsity
S Yin, D Kadetotad, B Yan, C Song, Y Chen, C Chakrabarti, J Seo
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 111-114, 2017
112017
Neuromorphic hardware accelerator for snn inference based on stt-ram crossbar arrays
SR Kulkarni, DV Kadetotad, S Yin, JS Seo, B Rajendran
2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019
82019
A 8.93-TOPS/W LSTM recurrent neural network accelerator featuring hierarchical coarse-grain sparsity with all parameters stored on-chip
D Kadetotad, V Berisha, C Chakrabarti, JS Seo
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019
82019
Joint optimization of quantization and structured sparsity for compressed deep neural networks
G Srivastava, D Kadetotad, S Yin, V Berisha, C Chakrabarti, J Seo
ICASSP 2019-2019 IEEE International Conference on Acoustics, Speech and …, 2019
82019
An 8.93 TOPS/W LSTM recurrent neural network accelerator featuring hierarchical coarse-grain sparsity for on-device speech recognition
D Kadetotad, S Yin, V Berisha, C Chakrabarti, J Seo
IEEE Journal of Solid-State Circuits 55 (7), 1877-1887, 2020
72020
A smart hardware security engine combining entropy sources of ECG, HRV, and SRAM PUF for authentication and secret key generation
SK Cherupally, S Yin, D Kadetotad, C Bae, SJ Kim, J Seo
IEEE Journal of Solid-State Circuits 55 (10), 2680-2690, 2020
62020
Memory compression in a deep neural network
J Seo, D Kadetotad, S Arunachalam, C Chakrabarti
US Patent 10,614,798, 2020
62020
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS
M Kim, A Mohanty, D Kadetotad, L Wei, X He, Y Cao, JS Seo
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (10), 3843-3853, 2019
52019
Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs
R Tapiador-Morales, A Rios-Navarro, A Linares-Barranco, M Kim, ...
International Work-Conference on Artificial Neural Networks, 271-282, 2017
5*2017
Peripheral circuit design considerations of neuro-inspired architectures
D Kadetotad, PY Chen, Y Cao, S Yu, J Seo
Neuro-inspired Computing Using Resistive Synaptic Devices, 167-182, 2017
42017
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