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Shinya Takamaeda-Yamazaki
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Pyverilog: A python-based hardware design processing toolkit for verilog hdl
S Takamaeda-Yamazaki
Applied Reconfigurable Computing: 11th International Symposium, ARC 2015 …, 2015
1742015
BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ...
IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017
1712017
QUEST: A 7.49 TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS
K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, J Kadomoto, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 216-218, 2018
992018
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ...
2017 Symposium on VLSI Circuits, C24-C25, 2017
932017
A cgra-based approach for accelerating convolutional neural networks
M Tanomoto, S Takamaeda-Yamazaki, J Yao, Y Nakashima
2015 IEEE 9th International Symposium on Embedded Multicore/Many-core …, 2015
682015
STATICA: A 512-spin 0.25 M-weight annealing processor with an all-spin-updates-at-once architecture for combinatorial optimization with complete spin–spin interactions
K Yamamoto, K Kawamura, K Ando, N Mertig, T Takemoto, M Yamaoka, ...
IEEE Journal of Solid-State Circuits 56 (1), 165-178, 2020
662020
QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS
K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, M Hamada, ...
IEEE Journal of Solid-State Circuits 54 (1), 186-196, 2018
572018
7.3 STATICA: A 512-spin 0.25 M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete …
K Yamamoto, K Ando, N Mertig, T Takemoto, M Yamaoka, H Teramoto, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 138-140, 2020
272020
STATICA: A 512-spin 0.25 M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete spin …
K Yamamoto, K Ando, N Mertig, T Takemoto, M Yamaoka, H Teramoto, ...
IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, 138-140, 2020
272020
An adaptive global and local tone mapping algorithm implemented on FPGA
P Ambalathankandy, M Ikebe, T Yoshida, T Shimada, S Takamaeda, ...
IEEE Transactions on Circuits and Systems for Video Technology 30 (9), 3015-3028, 2019
242019
A 96-MB 3D-stacked SRAM using inductive coupling with 0.4-V transmitter, termination scheme and 12: 1 SerDes in 40-nm CMOS
K Shiba, T Omori, K Ueyoshi, S Takamaeda-Yamazaki, M Motomura, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 692-703, 2020
232020
A time-division multiplexing Ising machine on FPGAs
K Yamamoto, W Huang, S Takamaeda-Yamazaki, M Ikebe, T Asai, ...
Proceedings of the 8th International Symposium on Highly Efficient …, 2017
192017
Real-time tone mapping: A survey and cross-implementation hardware benchmark
Y Ou, P Ambalathankandy, S Takamaeda, M Motomura, T Asai, M Ikebe
IEEE Transactions on Circuits and Systems for Video Technology 32 (5), 2666-2686, 2021
152021
Towards a low-power accelerator of many FPGAs for stencil computations
R Kobayashi, S Takamaeda-Yamazaki, K Kise
2012 Third International Conference on Networking and Computing, 343-349, 2012
152012
A multithreaded CGRA for convolutional neural network processing
K Ando, S Takamaeda-Yamazaki, M Ikebe, T Asai, M Motomura
Circuits and Systems 8 (6), 149-170, 2017
142017
Cprtree: A tree-based checkpointing architecture for heterogeneous fpga computing
HG Vu, S Kajkamhaeng, S Takamaeda-Yamazaki, Y Nakashima
2016 Fourth International Symposium on Computing and Networking (CANDAR), 57-66, 2016
132016
Hardware/algorithm co-optimization for fully-parallelized compact decision tree ensembles on FPGAs
T Ikeda, K Sakurada, A Nakamura, M Motomura, S Takamaeda-Yamazaki
Applied Reconfigurable Computing. Architectures, Tools, and Applications …, 2020
122020
A high performance and energy efficient microprocessor with a novel restricted dynamically reconfigurable accelerator
I Hida, S Takamaeda-Yamazaki, M Ikebe, M Motomura, T Asai
Circuits and Systems 8 (05), 134, 2017
122017
Real-time tone mapping: A state of the art report
Y Ou, P Ambalathankandy, M Ikebe, S Takamaeda, M Motomura, T Asai
arXiv preprint arXiv:2003.03074, 2020
112020
Dither nn: An accurate neural network with dithering for low bit-precision hardware
K Ando, K Ueyoshi, Y Oba, K Hirose, R Uematsu, T Kudo, M Ikebe, T Asai, ...
2018 International Conference on Field-Programmable Technology (FPT), 6-13, 2018
112018
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