Jung Ho Ahn
Jung Ho Ahn
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McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures
S Li, JH Ahn, RD Strong, JB Brockman, DM Tullsen, NP Jouppi
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
S Thoziyoor, N Muralimanohar, JH Ahn, NP Jouppi
Technical Report HPL-2008-20, HP Labs, 2008
Corona: System implications of emerging nanophotonic technology
D Vantrease, R Schreiber, M Monchiero, M McLaren, NP Jouppi, ...
International Symposium on Computer Architecture (ISCA), 153-164, 2008
Merrimac: Supercomputing with streams
WJ Dally, F Labonte, A Das, P Hanrahan, JH Ahn, J Gummaraju, M Erez, ...
Proceedings of the 2003 ACM/IEEE conference on Supercomputing, 35, 2003
Programmable stream processors
UJ Kapasi, S Rixner, WJ Dally, B Khailany, JH Ahn, P Mattson, JD Owens
Computer 36 (8), 54-62, 2003
HyperX: topology, routing, and packaging of efficient large-scale networks
JH Ahn, N Binkert, A Davis, M McLaren, RS Schreiber
Proceedings of the Conference on High Performance Computing Networking …, 2009
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
A Farmahini-Farahani, JH Ahn, K Morrow, NS Kim
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques
S Li, K Chen, JH Ahn, JB Brockman, NP Jouppi
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 694-701, 2011
A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies
S Thoziyoor, JH Ahn, M Monchiero, JB Brockman, NP Jouppi
2008 International symposium on computer architecture, 51-62, 2008
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing
S Li, JH Ahn, RD Strong, DM Brockman, Jay B., Tullsen, NP Jouppi
ACM Transactions on Architecture and Code Optimization 10 (1), 29, 2013
CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory
K Chen, S Li, N Muralimanohar, JH Ahn, JB Brockman, NP Jouppi
the Design, Automation & Test in Europe (DATE), 2012
Devices and architectures for photonic chip-scale integration
JH Ahn, M Fiorentino, RG Beausoleil, N Binkert, A Davis, D Fattal, ...
Applied Physics A 95 (4), 989-997, 2009
Evaluating the Imagine Stream Architecture
JH Ahn, WJ Dally, B Khailany, UJ Kapasi, A Das
International Symposium on Computer Architecture 32 (2), 12, 2004
Memory-centric system interconnect design with hybrid memory cubes
G Kim, J Kim, JH Ahn, J Kim
Proceedings of the 22nd international conference on Parallel architectures …, 2013
Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems
H Asghari-Moghaddam, YH Son, JH Ahn, NS Kim
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
Architecting to achieve a billion requests per second throughput on a single key-value store server platform
S Li, H Lim, VW Lee, JH Ahn, A Kalia, M Kaminsky, DG Andersen, S O, ...
ISCA, 476-488, 2015
Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations
YH Son, S O, Y Ro, JW Lee, JH Ahn
Proceedings of the 40th Annual International Symposium on Computer …, 2013
McSimA+: A Manycore Simulator with Application-level+ Simulation and Detailed Microarchitecture Modeling
JH Ahn, S Li, S O, NP Jouppi
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013
Future scaling of processor-memory interfaces
JH Ahn, NP Jouppi, C Kozyrakis, J Leverich, RS Schreiber
Proceedings of the Conference on High Performance Computing Networking …, 2009
A nanophotonic interconnect for high-performance many-core computation
RG Beausoleil, J Ahn, N Binkert, A Davis, D Fattal, M Fiorentino, ...
2008 16th IEEE Symposium on High Performance Interconnects, 182-189, 2008
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