| Strain-compensating fill patterns for controlling semiconductor chip package interactions VW Ryan US Patent 8,441,131, 2013 | 130 | 2013 |
| Bond pad design for integrated circuits S Chittipeddi, V Ryan US Patent 5,986,343, 1999 | 87 | 1999 |
| Process for fabricating copper interconnect for ULSI integrated circuits VW Ryan US Patent 6,410,435, 2002 | 65 | 2002 |
| Interconnections to copper IC's RS Moyer, VW Ryan US Patent 6,620,720, 2003 | 51 | 2003 |
| CVD Co and its application to Cu damascene interconnections T Nogami, J Maniscalco, A Madan, P Flaitz, P DeHaven, C Parks, L Tai, ... 2010 IEEE International Interconnect Technology Conference, 1-3, 2010 | 40 | 2010 |
| Stress migration test structure and method therefor HS Fetterman, V Ryan US Patent 6,747,445, 2004 | 37 | 2004 |
| Bond pad design for integrated circuits S Chittipeddi, V Ryan US Patent 6,207,547, 2001 | 31 | 2001 |
| Process for fabricating copper interconnect for ULSI integrated circuits V Ryan US Patent App. 10/120,707, 2002 | 28 | 2002 |
| Integrated circuit having stress migration test structure and method therefor HS Fetterman, V Ryan US Patent 6,683,465, 2004 | 22 | 2004 |
| Bond pad for a flip-chip package S Chittipeddi, V Ryan US Patent 6,087,732, 2000 | 21 | 2000 |
| CPI Challenges to BEOL at 28nm Node and Beyond V Ryan, D Breuer, H Geisler, D Kioussis, MU Lehr, J Paul, K Machani, ... 2012 IEEE International Reliability Physics Symposium (IRPS), 2E. 1.1-2E. 1.6, 2012 | 19 | 2012 |
| Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink VD Archer III, K Azimi, DP Chesire, WK Gladden, SH Kang, T Kook, ... US Patent 7,429,502, 2008 | 19 | 2008 |
| Stress migration evaluation method VW Ryan US Patent 5,930,587, 1999 | 19 | 1999 |
| Aluminum metallization doped with iron and copper to prevent electromigration VW Ryan, RJ Schutz US Patent 5,243,221, 1993 | 18 | 1993 |
| Size determination of Streptococcus mutans 10499 by laser light scattering V Ryan, TR Hart, R Schiller Biophysical journal 31 (3), 313-324, 1980 | 18 | 1980 |
| Heat sink formed of multiple metal layers on backside of integrated circuit die V Ryan, RH Shanaman III US Patent 7,745,927, 2010 | 17 | 2010 |
| Multi-layer barrier layer stacks for interconnect structures VW Ryan, X Zhang, PR Besser US Patent 8,772,158, 2014 | 16 | 2014 |
| Aluminum metallization for semiconductor devices VW Ryan, RJ Schutz US Patent 4,975,389, 1990 | 14 | 1990 |
| Devices involving silicon glasses VW Ryan, G Smolinsky US Patent 4,826,709, 1989 | 14 | 1989 |
| Bond pad for a flip chip package, and method of forming the same S Chittipeddi, V Ryan US Patent 6,187,658, 2001 | 13 | 2001 |
