| First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices R Delhougne, A Arreghini, E Rosseel, A Hikavyy, E Vecchio, L Zhang, ... 2018 IEEE Symposium on VLSI Technology, 203-204, 2018 | 143 | 2018 |
| Punchthrough-Diode-Based Bipolar RRAM Selector by Si Epitaxy VSS Srinivasan, S Chopra, P Karkare, P Bafna, S Lashkare, P Kumbhare, ... Electron Device Letters, IEEE 33 (10), 1396-1398, 2012 | 110 | 2012 |
| Charge Trapping Analysis of Metal/Al2O3/SiO2/Si, Gate Stack for Emerging Embedded Memories R Khosla, EG Rolseth, P Kumar, SS Vadakupudhupalayam, SK Sharma, ... IEEE Transactions on Device and Materials Reliability 17 (1), 80-89, 2017 | 44 | 2017 |
| Dosimetry aspects of hafnium oxide metal-oxide-semiconductor (MOS) capacitor VSS Srinivasan, A Pandya Thin Solid Films 520 (1), 574-577, 2011 | 32 | 2011 |
| The impact of npn selector-based bipolar RRAM cross-point on array performance R Mandapati, AS Borkar, VSS Srinivasan, P Bafna, P Karkare, S Lodha, ... Electron Devices, IEEE Transactions on 60 (10), 3385-3392, 2013 | 23 | 2013 |
| Gamma irradiation study of tin oxide thin films for dosimetric applications VS Senthil Srinivasan, MK Patra, VS Choudhary, A Pandya Journal of optoelectronics and Advanced Materials 9, 2007 | 19 | 2007 |
| A bipolar RRAM selector with designable polarity dependent on-voltage asymmetry S Lashkare, P Karkare, P Bafna, MVS Raju, VSS Srinivasan, S Lodha, ... Memory Workshop (IMW), 2013 5th IEEE International, 178-181, 2013 | 17 | 2013 |
| Surround gate transistor with epitaxially grown Si pillar and simulation study on soft error and rowhammer tolerance for DRAM JW Han, J Kim, D Beery, KD Bozdag, P Cuevas, A Levi, I Tain, K Tran, ... IEEE Transactions on Electron Devices 68 (2), 529-534, 2021 | 16 | 2021 |
| On pairing of bipolar RRAM memory with NPN selector based on set/reset array power considerations R Mandapati, A Borkar, VSS Srinivasan, P Bafna, P Karkare, S Lodha, ... Nanotechnology, IEEE Transactions on 12 (6), 1178-1184, 2013 | 14 | 2013 |
| Trap Reduction and Performances Improvements Study after High Pressure Anneal Process on Single Crystal Channel 3D NAND Devices AF A Subirats, A Arreghini, R Delhougne, E Rosseel, A Hikavyy, L Breuil, S ... 2018 IEEE International Electron Devices Meeting (IEDM), 25.4. 1-25.4. 4, 2018 | 12 | 2018 |
| Epitaxial Si punch-through based selector for bipolar RRAM P Bafna, P Karkare, S Srinivasan, S Chopra, S Lashkare, Y Kim, ... 70th Device Research Conference, 115-116, 2012 | 12 | 2012 |
| Understanding and variability of lateral charge migration in 3D CT-NAND flash with and without band-gap engineered barriers A Padovani, M Pesic, MA Kumar, P Blomme, A Subirats, ... 2019 IEEE International Reliability Physics Symposium (IRPS), 1-8, 2019 | 11 | 2019 |
| Effect of top metal contact on electrical transport through individual multiwalled carbon nanotubes N Kulshrestha, A Misra, S Srinivasan, KS Hazra, R Bajpai, S Roy, ... Applied Physics Letters 97 (22), 222102, 2010 | 11 | 2010 |
| Improvement of conduction in 3-D NAND memory devices by channel and junction optimization A Arreghini, K Banerjee, D Verreck, SV Palayam, E Rosseel, L Nyns, ... 2019 IEEE 11th International Memory Workshop (IMW), 1-4, 2019 | 10 | 2019 |
| Impact of SiON tunnel layer composition on 3D NAND cell performance L Breuil, L Nyns, K Banerjee, SV Palayam, A Subirats, O Richard, ... 2019 IEEE 11th International Memory Workshop (IMW), 2019 | 9 | 2019 |
| S-parameter characterization and lumped-element modelling of millimeter-wave single-drift impact-ionization avalanche transit-time diode W Zhang, Y Yamamoto, M Oehme, K Matthies, AI Raju, ... Japanese Journal of Applied Physics 55 (04EF03), 1-6, 2016 | 9 | 2016 |
| In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices CL Tan, S Lavizzari, P Blomme, L Breuil, G Vecchio, F Sebaai, ... Memory Workshop (IMW), 2017 IEEE International, 2017 | 8 | 2017 |
| Contact resistivities of antimony-doped n-type Ge1−x Sn x VSS Srinivasan, IA Fischer, L Augel, A Hornung, R Koerner, K Kostecki, ... Semiconductor Science and Technology 31 (8), 08LT01, 2016 | 8 | 2016 |
| On pairing bipolar RRAM memory element with novel punch-through diode based selector: Compact modeling to array performance R Mandapati, A Borkar, VSS Srinivasan, PBP Karkare, S Lodha, ... Nanoelectronics Conference (INEC), 2013 IEEE 5th International, 309-312, 2013 | 6 | 2013 |
| Comparison of novel punch-through diode (NPN) selector with MIM selector for bipolar RRAM S Deshmukh, R Mandapati, S Lashkare, A Borkar, VSS Srivinasan, ... Non-Volatile Memory Technology Symposium (NVMTS), 2012 12th Annual, 51-54, 2012 | 6 | 2012 |
Udayan GangulyProfessor, Electrical Engineering, IIT BombayVerified email at ee.iitb.ac.in
