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Chen-Kai  Hsu
Chen-Kai Hsu
Analog Devices, inc.
Verified email at utexas.edu
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Cited by
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Year
A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier
X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, S Li, ...
IEEE Journal of Solid-State Circuits 55 (12), 3248-3259, 2020
742020
9.5 a 13.5 b-ENOB second-order noise-shaping SAR with PVT-robust closed-loop dynamic amplifier
X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 162-164, 2020
452020
A 90-dB-SNDR calibration-free fully passive noise-shaping SAR ADC with 4× passive gain and second-order DAC mismatch error shaping
J Liu, X Wang, Z Gao, M Zhan, X Tang, CK Hsu, N Sun
IEEE Journal of Solid-State Circuits 56 (11), 3412-3423, 2021
312021
Error-feedback mismatch error shaping for high-resolution data converters
J Liu, CK Hsu, X Tang, S Li, G Wen, N Sun
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (4), 1342-1354, 2018
302018
3.4 A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor
L Shen, Y Shen, X Tang, CK Hsu, W Shi, S Li, W Zhao, A Mukherjee, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 64-66, 2019
202019
A 77.1-dB-SNDR 6.25-MHz-BW pipeline SAR ADC with enhanced interstage gain error shaping and quantization noise shaping
CK Hsu, X Tang, J Liu, R Xu, W Zhao, A Mukherjee, TR Andeen, N Sun
IEEE Journal of Solid-State Circuits 56 (3), 739-749, 2020
182020
A pipeline SAR ADC with second-order interstage gain error shaping
CK Hsu, TR Andeen, N Sun
IEEE Journal of Solid-State Circuits 55 (4), 1032-1042, 2020
162020
A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping
CK Hsu, N Sun
2019 Symposium on VLSI Circuits, C68-C69, 2019
122019
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS
A Mukherjee, M Gandara, X Yang, L Shen, X Tang, CK Hsu, N Sun
IEEE Journal of Solid-State Circuits 56 (2), 476-487, 2020
112020
Design Tradeoffs for a CT-ΔΣ ADC with Hybrid Active–Passive Filter and FIR DAC in 40-nm CMOS
A Mukherjee, X Tang, CK Hsu, N Sun
IEEE Solid-State Circuits Letters 3, 214-217, 2020
62020
A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology
CK Hsu, TC Lee
2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015
52015
A 77.1-dB 6.25-MHz-BW pipeline SAR ADC with enhanced interstage gain error shaping and quantization error shaping
CK Hsu, X Tang, W Zhao, R Xu, A Mukherjee, TR Andeen, N Sun
2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020
42020
Single-event upset responses of metal–oxide–metal capacitors and diodes used in bulk 65-nm CMOS analog circuits
R Xu, CK Hsu, S Kalani, J Ban, Q Wang, I Ochoa, C Burton, M Ünal, ...
IEEE Transactions on Nuclear Science 67 (4), 698-707, 2020
32020
COLUTA: Custom 8-Channel 15-bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout
R Xu, J Ban, S Kalani, CK Hsu, S Ray, B Kirby, G Matos, J Gonski, A Smith, ...
2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC …, 2022
12022
Pipeline analog-to-digital converter design in scaled CMOS technology
CK Hsu
2021
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