Praveen Ghanta
Praveen Ghanta
Verified email at synopsys.com
Title
Cited by
Cited by
Year
Stochastic analysis of interconnect performance in the presence of process variations
J Wang, P Ghanta, S Vrudhula
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
1132004
Hermite polynomial based interconnect analysis in the presence of process variations
S Vrudhula, JM Wang, P Ghanta
IEEE Transactions on Computer-Aided Design of Integrated circuits and …, 2006
1092006
A framework for statistical timing analysis using non-linear delay and slew models
S Bhardwaj, P Ghanta, S Vrudhula
2006 IEEE/ACM International Conference on Computer Aided Design, 225-230, 2006
682006
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits
S Bhardwaj, S Vrudhula, P Ghanta, Y Cao
Proceedings of the 43rd annual Design Automation Conference, 791-796, 2006
652006
Stochastic power grid analysis considering process variations
P Ghanta, S Vrudhula, R Panda, J Wang
Design, Automation and Test in Europe, 964-969, 2005
612005
Simultaneous multi-corner static timing analysis using samples-based static timing infrastructure
P Ghanta, A Goel, FP Taraporevala, M Ovchinnikov, J Liu, K Kucukcakar
US Patent 8,615,727, 2013
312013
Variational interconnect delay metrics for statistical timing analysis
P Ghanta, S Vrudhula
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-24, 2006
172006
Stochastic variational analysis of large power grids considering intra-die correlations
P Ghanta, S Vrudhula, S Bhardwaj, R Panda
2006 43rd ACM/IEEE Design Automation Conference, 211-216, 2006
162006
A methodology for characterization of large macro cells and IP blocks considering process variations
A Goel, S Vrudhula, F Taraporevala, P Ghanta
9th International Symposium on Quality Electronic Design (isqed 2008), 200-206, 2008
152008
Statistical timing models for large macro cells and IP blocks considering process variations
A Goel, S Vrudhula, F Taraporevala, P Ghanta
IEEE transactions on semiconductor manufacturing 22 (1), 3-11, 2009
142009
Analysis of power supply noise in the presence of process variations
P Ghanta, S Vrudhula
IEEE Design & Test of Computers 24 (3), 256-266, 2007
112007
Information display device and method for displaying information
Y Hirose, S Yoshizawa
US Patent App. 10/185,795, 2003
102003
Systems and methods for statistical static timing analysis
I Keller, P Ghanta, AK Mishra
US Patent 10,185,795, 2019
52019
Analytical expressions for phase noise eigenfunctions of LC oscillators
P Ghanta, Z Li, J Roychowdhury
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004
52004
Systems and methods for statistical static timing analysis
I Keller, P Ghanta, AK Mishra
US Patent 10,073,934, 2018
42018
Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation
I Keller, P Ghanta, M Chetin
US Patent 10,430,536, 2019
32019
Method of evaluating integrated circuit system performance using orthogonal polynomials
P Ghanta, S Vrudhula, S Bhardwaj
US Patent 7,630,852, 2009
32009
Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design
M Chetin, I Keller, P Ghanta
US Patent 10,275,554, 2019
22019
Computation of joint timing yield of sequential networks considering process variations
A Goel, S Bhardwaj, P Ghanta, S Vrudhula
International Workshop on Power and Timing Modeling, Optimization and …, 2007
12007
Variational Analysis of Interconnects & Power Grids based on Orthogonal Polynomial Expansions
P Ghanta, S Bhardwaj, S Vrudhula
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