Follow
Albert Magyar
Albert Magyar
Graduate Student Researcher, UC Berkeley
Verified email at berkeley.edu
Title
Cited by
Cited by
Year
The rocket chip generator
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016
547*2016
Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
A Izraelevitz, J Koenig, P Li, R Lin, A Wang, A Magyar, D Kim, C Schmidt, ...
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 209-216, 2017
1232017
Chipyard: Integrated design, simulation, and implementation framework for custom socs
A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ...
IEEE Micro 40 (4), 10-21, 2020
772020
Evaluation of large volume SrI2(Eu) scintillator detectors
BW Sturm, NJ Cherepy, OB Drury, PA Thelin, SE Fisher, AF Magyar, ...
IEEE Nuclear Science Symposuim & Medical Imaging Conference, 1607-1611, 2010
212010
Z-scale: Tiny 32-bit RISC-V systems
Y Lee, A Ou, A Magyar
OpenRISC Conf, 2015
172015
A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V microprocessor using scalable dynamic leakage-suppression logic
DS Truesdell, J Breiholz, S Kamineni, N Liu, A Magyar, BH Calhoun
IEEE Solid-State Circuits Letters 2 (8), 57-60, 2019
152019
Golden gate: Bridging the resource-efficiency gap between ASICs and FPGA prototypes
A Magyar, D Biancolin, J Koenig, S Seshia, J Bachrach, K Asanović
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
122019
The Rocket Chip Generator: Tech. Rep. UCB/EECS-2016-17
K Asanović, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
EECS Department, University of California Berkeley, 2016
82016
Z-scale: Tiny 32-bit risc-v systems with updates to the rocket chip generator
A Magyar, Y Lee, A Ou
The International House, 2015
62015
Cyclist: Accelerating hardware development
J Bachrach, A Magyar, P Dabbelt, P Li, R Lin, K Asanovic
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD …, 2017
32017
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim
D Biancolin, A Magyar, S Karandikar, A Amid, B Nikolić, J Bachrach, ...
IEEE Micro 41 (4), 58-66, 2021
12021
Improving FPGA Simulation Capacity with Automatic Resource Multi-Threading
AF Magyar
PhD thesis. EECS Department, University of California, Berkeley, 2021
12021
Chipyard-An integrated SoC research and implementation environment
A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ...
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
12020
Accelerator Integration for Open-Source SoC Design
D Biancolin, A Magyar, S Karandikar, A Amid, B Nikolic, J Bachrach, ...
IEEE MICRO 41 (4), 58-66, 2021
2021
Z-scale: Tiny 32-bit RISC-V systems
Y Lee, A Ou, A Magyar
OpenRISC Conf, 2015
2015
The system can't perform the operation now. Try again later.
Articles 1–15