| The rocket chip generator K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016 | 854* | 2016 |
| Chipyard: Integrated design, simulation, and implementation framework for custom socs A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ... IEEE Micro 40 (4), 10-21, 2020 | 216 | 2020 |
| Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations A Izraelevitz, J Koenig, P Li, R Lin, A Wang, A Magyar, D Kim, C Schmidt, ... 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 209-216, 2017 | 216 | 2017 |
| Golden Gate: Bridging the resource-efficiency gap between ASICs and FPGA prototypes A Magyar, D Biancolin, J Koenig, S Seshia, J Bachrach, K Asanović 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 27 | 2019 |
| Evaluation of large volume SrI2(Eu) scintillator detectors BW Sturm, NJ Cherepy, OB Drury, PA Thelin, SE Fisher, AF Magyar, ... IEEE Nuclear Science Symposuim & Medical Imaging Conference, 1607-1611, 2010 | 25 | 2010 |
| A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V microprocessor using scalable dynamic leakage-suppression logic DS Truesdell, J Breiholz, S Kamineni, N Liu, A Magyar, BH Calhoun IEEE Solid-State Circuits Letters 2 (8), 57-60, 2019 | 21 | 2019 |
| Z-scale: Tiny 32-bit RISC-V systems Y Lee, A Ou, A Magyar OpenRISC Conf, 2015 | 20 | 2015 |
| The Rocket Chip Generator: Tech. Rep. UCB/EECS-2016-17 K Asanović, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... EECS Department, University of California Berkeley, 2016 | 8 | 2016 |
| Accessible, FPGA resource-optimized simulation of multiclock systems in firesim D Biancolin, A Magyar, S Karandikar, A Amid, B Nikolić, J Bachrach, ... IEEE Micro 41 (4), 58-66, 2021 | 6 | 2021 |
| Z-scale: Tiny 32-bit risc-v systems with updates to the rocket chip generator A Magyar, Y Lee, A Ou The International House, 2015 | 6 | 2015 |
| Chipyard-An integrated SoC research and implementation environment A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 4 | 2020 |
| Cyclist: Accelerating hardware development J Bachrach, A Magyar, P Dabbelt, P Li, R Lin, K Asanovic 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD …, 2017 | 4 | 2017 |
| Improving FPGA Simulation Capacity with Automatic Resource Multi-Threading AF Magyar eScholarship, University of California, 2021 | 1 | 2021 |
| Accelerator Integration for Open-Source SoC Design D Biancolin, A Magyar, S Karandikar, A Amid, B Nikolic, J Bachrach, ... IEEE MICRO 41 (4), 58-66, 2021 | | 2021 |
| Z-scale: Tiny 32-bit RISC-V systems Y Lee, A Ou, A Magyar OpenRISC Conf, 2015 | | 2015 |
