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Ahmed S. Eissa
Ahmed S. Eissa
Digital Verification Engineer
Verified email at alexu.edu.eg
Title
Cited by
Cited by
Year
RVNoC: A framework for generating RISC-V NoC-based MPSoC
MA Elmohr, AS Eissa, M Ibrahim, M Khamis, S El-Ashry, A Shalaby, ...
2018 26th Euromicro International Conference on Parallel, Distributed and …, 2018
172018
A reusable verification environment for NoC platforms using UVM
AS Eissa, MA Ibrahem, MA Elmohr, Y Zamzam, A El-Yamany, S El-Ashry, ...
IEEE EUROCON 2017-17th International Conference on Smart Technologies, 239-242, 2017
142017
SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture
AS Eissa, MA Elmohr, MA Saleh, KE Ahmed, MM Farag
2016 IEEE 27th International Conference on Application-specific Systems …, 2016
122016
Hardware implementation of a SHA-3 application-specific instruction set processor
MA Elmohr, MA Saleh, AS Eissa, KE Ahmed, MM Farag
2016 28th International Conference on Microelectronics (ICM), 109-112, 2016
102016
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Articles 1–4