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Peter Smeys
Peter Smeys
Unknown affiliation
Verified email at smeys.com
Title
Cited by
Cited by
Year
Integrated circuit micro-module
P Smeys, P Johnson, P Deane, RR Razouk
US Patent 7,902,661, 2011
832011
Method and system for forming a capacitive micromachined ultrasonic transducer
P Smeys, P Johnson, G Percin
US Patent 8,222,065, 2012
802012
Influence of process-induced stress on device characteristics and its impact on scaled device performance
P Smeys, PB Griffin, ZU Rek, I De Wolf, KC Saraswat
IEEE Transactions on Electron Devices 46 (6), 1245-1252, 1999
781999
High-performance sub-0.08/spl mu/m CMOS with dual gate oxide and 9.7 ps inverter delay
M Hargrove, S Crowder, E Nowak, R Logan, LK Han, H Ng, A Ray, ...
International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998
781998
A 0.13-/spl mu/m SOI CMOS technology for low-power digital and RF applications
N Zamdmer, A Ray, JO Plouchart, L Wagner, N Fong, KA Jenkins, W Jin, ...
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2001
762001
Integrated circuit micro-module
A Mohan, P Smeys
US Patent 8,187,920, 2012
692012
High frequency semiconductor transformer
DW Lee, P Smeys, A Mohan, PJ Hopper
US Patent 8,130,067, 2012
452012
SOI CMOS dynamic circuits having threshold voltage control
F Assaderaghi, K Bernstein, MJ Hargrove, NJ Rohrer, P Smeys
US Patent 6,433,587, 2002
412002
Fuse structure with thermal and crack-stop protection
JW Adkisson, E Maciejewski, P Smeys, AK Stamper
US Patent 6,653,710, 2003
392003
Analysis of integrated solenoid inductor with closed magnetic core
JM Wright, DW Lee, A Mohan, A Papou, P Smeys, SX Wang
IEEE transactions on magnetics 46 (6), 2387-2390, 2010
372010
Electrical fuses employing reverse biasing to enhance programming
SK Iyer, P Smeys, C Narayan, S Iyer, A Brintzinger
US Patent 6,323,535, 2001
362001
A high performance 0.13/spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
P Smeys, V McGahay, I Yang, J Adkisson, K Beyer, O Bula, Z Chen, ...
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2000
362000
CMOS-MEMS integrated device including multiple cavities at different controlled pressures and methods of manufacture
D Lee, S Jongwoo, JI Shin, P Smeys, M Lim
US Patent 9,738,512, 2017
352017
SOI Wafer and Method of Forming the SOI Wafer with Through the Wafer Contacts and Trench Based Interconnect Structures that Electrically Connect the Through the Wafer Contacts
P Smeys, P Johnson, PJ Hopper, W French
US Patent App. 12/768,295, 2011
352011
Triple oxide fill for trench isolation
KD Beyer, PA O'neil, DA Ryan, P Smeys, E Leobandung
US Patent 6,825,097, 2004
342004
On-chip inductor for high current applications
PJ Hopper, P Smeys, A Papou
US Patent 7,936,246, 2011
332011
Galvanic isolation transformer
W French, PJ Hopper, P Smeys, A Gabrys, DI Anderson
US Patent App. 12/827,316, 2012
302012
Magnetically enhanced power inductor with self-aligned hard axis magnetic core produced in an applied magnetic field using a damascene process sequence
P Smeys, P Johnson, A Papou
US Patent 8,407,883, 2013
282013
Integrated circuit micro-module
P Smeys, P Johnson, P Deane
US Patent 7,842,544, 2010
272010
The influence of oxidation-induced stress on the generation current and its impact on scaled device performance
P Smeys, PB Griffin, ZU Rek, I De Wolf, KC Saraswat
International Electron Devices Meeting. Technical Digest, 709-712, 1996
261996
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