Steven Bentley
Steven Bentley
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Cited by
Cited by
Continuous flow in open microfluidics using controlled evaporation
M Zimmermann, S Bentley, H Schmid, P Hunziker, E Delamarche
Lab on a Chip 5 (12), 1355-1359, 2005
Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts
JH Zhang, C Radens, SJ Bentley, BA Cohen, KY Lim
US Patent 9,530,866, 2016
Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
J Frougier, MG Sung, R Xie, C Park, S Bentley
US Patent 9,947,804, 2018
Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device
SJ Bentley, JH Zhang, KY Lim, H Niimi
US Patent 9,640,636, 2017
Self-aligned gate-first VFETs using a gate spacer recess
JH Zhang, KY Lim, SJ Bentley, C Park
US Patent 9,536,793, 2017
Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI
J Zhang, S Bentley, KY Lim
US Patent 9,773,708, 2017
Methods of forming vertical transistor devices with self-aligned replacement gate structures
JH Zhang, C Radens, SJ Bentley, BA Cohen, KY Lim
US Patent 9,530,863, 2016
Electron Mobility in Surface- and Buried-Channel FlatbandMOSFETs With ALDGate Dielectric
SJ Bentley, M Holland, X Li, GW Paterson, H Zhou, O Ignatova, ...
IEEE Electron Device Letters 32 (4), 494-496, 2011
Complementary FETs with wrap around contacts and method of forming same
J Frougier, R Xie, PH Suvarna, H Niimi, SJ Bentley, A Razavieh
US Patent 10,192,867, 2019
Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process
BJ Pawlak, S Bentley, A Jacob
US Patent 8,716,156, 2014
Methods of forming substrates comprised of different semiconductor materials and the resulting device
BJ Pawlak, S Bentley, A Jacob
US Patent 9,368,578, 2016
Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device
J Frougier, A Razavieh, R Xie, S Bentley
US Patent 9,991,352, 2018
Method and structure to control channel length in vertical FET device
S Bentley, R Xie
US Patent 9,972,494, 2018
Methods of forming a gate structure on a vertical transistor device
JH Zhang, SJ Bentley, KY Lim
US Patent 9,799,751, 2017
Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al2O3 formed by thermal oxidation of evaporated aluminium
S Taking, A Banerjee, H Zhou, X Li, AZ Khokhar, R Oxland, I McGregor, ...
Electronics letters 46 (4), 301-302, 2010
Methods of forming epitaxial semiconductor material on source/drain regions of a finfet semiconductor device and the resulting devices
JA Fronheiser, BV Krishnan, MK Akarvardar, S Bentley, AP Jacob, J Liu
US Patent App. 14/164,934, 2015
Work function metal patterning for NP space between active nanostructures
D Chanemougame, SR Soss, SJ Bentley, J Frougier, R Xie
US Patent 10,510,620, 2019
Metal layer routing level for vertical FET SRAM and logic cell scaling
S Bentley, BC Paul
US Patent 9,825,032, 2017
Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor
R Xie, S Soss, S Bentley, D Chanemougame, J Frougier, P Bipul, ...
US Patent 11,201,152, 2021
Self-aligned dual-height isolation for bulk FinFET
MK Akarvardar, SJ Bentley, K Cheng, BB Doris, J Fronheiser, AP Jacob, ...
US Patent 9,324,790, 2016
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