| SEERAD: A high speed yet energy-efficient rounding-based approximate divider R Zendegani, M Kamal, A Fayyazi, A Afzali-Kusha, S Safari, M Pedram 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 64 | 2016 |
| An ultra low-power memristive neuromorphic circuit for Internet of Things smart sensors A Fayyazi, M Ansari, M Kamal, A Afzali-Kusha, M Pedram IEEE Internet of Things Journal 5 (2), 1011-1022, 2018 | 46 | 2018 |
| PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits M Ansari, A Fayyazi, A Banagozar, MA Maleki, M Kamal, A Afzali-Kusha, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 27 | 2017 |
| Deep learning-based circuit recognition using sparse mapping and level-dependent decaying sum circuit representations A Fayyazi, S Shababi, P Nuzzo, S Nazarian, M Pedram 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 638-641, 2019 | 23 | 2019 |
| VeriSFQ: A semi-formal verification framework and benchmark for single flux quantum technology AD Wong, K Su, H Sun, A Fayyazi, M Pedram, S Nazarian 20th International Symposium on Quality Electronic Design (ISQED), 224-230, 2019 | 22 | 2019 |
| SystemVerilog modeling of SFQ and AQFP circuits RN Tadros, A Fayyazi, M Pedram, PA Beerel IEEE Transactions on Applied Superconductivity 30 (2), 1-13, 2019 | 20 | 2019 |
| Synergiclearning: Neural network-based feature extraction for highly-accurate hyperdimensional learning M Nazemi, A Fayyazi, A Esmaili, M Pedram Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 18 | 2020 |
| OCTAN: An on-chip training algorithm for memristive neuromorphic circuits M Ansari, A Fayyazi, M Kamal, A Afzali-Kusha, M Pedram IEEE Transactions on Circuits and Systems I: Regular Papers 66 (12), 4687-4698, 2019 | 15 | 2019 |
| Hardware Architectures for Deep Learning M Daneshtalab, M Modarressi Institution of Engineering and Technology, 2020 | 12 | 2020 |
| NullaNet Tiny: Ultra-low-latency DNN inference through fixed-function combinational logic M Nazemi, A Fayyazi, A Esmaili, A Khare, SN Shahsavani, M Pedram 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021 | 10 | 2021 |
| Better than worst-case decoding for quantum error correction GS Ravi, JM Baker, A Fayyazi, SF Lin, A Javadi-Abhari, M Pedram, ... Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 9 | 2023 |
| qEC: A logical equivalence checking framework targeting SFQ superconducting circuits A Fayyazi, S Nazarian, M Pedram 2019 IEEE International Superconductive Electronics Conference (ISEC), 1-3, 2019 | 8 | 2019 |
| CSrram: Area-efficient low-power ex-situ training framework for memristive neuromorphic circuits based on clustered sparsity A Fayyazi, S Kundu, S Nazarian, PA Beerel, M Pedram 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 465-470, 2019 | 8 | 2019 |
| Results from the coldflux superconductor integrated circuit design tool project CJ Fourie, K Jackman, J Delport, L Schindler, T Hall, P Febvre, ... IEEE Transactions on Applied Superconductivity, 2023 | 6 | 2023 |
| Better Than Worst-Case Decoding for Quantum Error Correction G Subramanian Ravi, JM Baker, A Fayyazi, S Fuhui Lin, A Javadi-Abhari, ... arXiv e-prints, arXiv: 2208.08547, 2022 | 6* | 2022 |
| ESPRESSO-GPU: blazingly fast two-level logic minimization H Kanakia, M Nazemi, A Fayyazi, M Pedram 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 6 | 2021 |
| qCG: A low-power multi-domain SFQ logic design and verification framework S Nazarian, A Fayyazi, M Pedram 2019 IEEE 37th International Conference on Computer Design (ICCD), 446-449, 2019 | 6 | 2019 |
| Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations. In 2019 Design, Automation Test in Europe Conference … A Fayyazi, S Shababi, P Nuzzo, S Nazarian, M Pedram IEEE, 2019 | 6 | 2019 |
| Qmc: A formal model checking verification framework for superconducting logic M Munir, A Gopikanna, A Fayyazi, M Pedram, S Nazarian Proceedings of the 2021 on Great Lakes Symposium on VLSI, 259-264, 2021 | 5 | 2021 |
| A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning K Singh, R Gupta, V Gupta, A Fayyazi, M Pedram, S Nazarian Proceedings of the 2019 on Great Lakes Symposium on VLSI, 367-370, 2019 | 5 | 2019 |
Massoud PedramCharles Lee Powell Professor of Electrical Engineering & Computer Science, Univ of SouthernVerified email at usc.edu
