| SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture AS Eissa, MA Elmohr, MA Saleh, KE Ahmed, MM Farag Application-specific Systems, Architectures and Processors (ASAP), 2016 IEEE …, 2016 | 12 | 2016 |
| Hardware implementation of a SHA-3 application-specific instruction set processor MA Elmohr, MA Saleh, AS Eissa, KE Ahmed, MM Farag Microelectronics (ICM), 2016 28th International Conference on, 109-112, 2016 | 10 | 2016 |
