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Charles Yount
Charles Yount
Principal Engineer, Intel Corp.
Verified email at acm.org
Title
Cited by
Cited by
Year
Architecture and performance of Devito, a system for automated stencil computation
F Luporini, M Louboutin, M Lange, N Kukreja, P Witte, J Hückelheim, ...
ACM Transactions on Mathematical Software (TOMS) 46 (1), 1-28, 2020
832020
Vector friendly instruction format and execution thereof
RC Valentine, JC San Adrian, RE Sans, RD Cavin, BL Toll, SG Duran, ...
US Patent App. 13/976,707, 2013
762013
A methodology for the rapid injection of transient hardware errors
CR Yount, DP Siewiorek
IEEE Transactions on Computers 45 (8), 881-891, 1996
691996
Using model trees for computer architecture performance analysis of software applications
EM Ould-Ahmed-Vall, J Woodlee, C Yount, KA Doshi, S Abraham
2007 IEEE International Symposium on Performance Analysis of Systems …, 2007
642007
YASK—Yet another stencil kernel: A framework for HPC stencil code-generation and tuning
C Yount, J Tobin, A Breuer, A Duran
2016 Sixth International Workshop on Domain-Specific Languages and High …, 2016
602016
Vector folding: Improving stencil performance via multi-dimensional simd-vector representation
C Yount
2015 IEEE 17th International Conference on High Performance Computing and …, 2015
462015
Characterization and optimization methodology applied to stencil computations
C Andreolli, P Thierry, L Borges, G Skinner, C Yount, J Jeffers, J Reinders
High Performance Parallelism Pearls, 377-396, 2015
402015
Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gathering
E Ould-Ahmed-Vall, KA Doshi, CR Yount, S Sair
US Patent 9,747,101, 2017
362017
Instruction and logic to provide vector horizontal majority voting functionality
E Ould-Ahmed-Vall, KA Doshi, S Sair, CR Yount
US Patent 9,448,794, 2016
282016
Efficient zero-based decompression
E Ould-Ahmed-Vall, S Sair, KA Doshi, CR Yount, BL Toll
US Patent 9,575,757, 2017
272017
Effective use of large high-bandwidth memory caches in HPC stencil computation via temporal wave-front tiling
C Yount, A Duran
2016 7th International Workshop on Performance Modeling, Benchmarking and …, 2016
272016
Instruction and logic to provide stride-based vector load-op functionality with mask duplication
E Ould-Ahmed-Vall, KA Doshi, S Sair, CR Yount
US Patent 9,804,844, 2017
252017
Multi-level spatial and temporal tiling for efficient HPC stencil computation on many-core processors with large shared caches
C Yount, A Duran, J Tobin
Future Generation Computer Systems 92, 903-919, 2019
182019
Characterization of SPEC CPU2006 and SPEC OMP2001: Regression models and their transferability
EM Ould-Ahmed-Vall, KA Doshi, C Yount, J Woodlee
ISPASS 2008-IEEE International Symposium on Performance Analysis of Systems …, 2008
182008
Accelerating seismic simulations using the intel xeon phi knights landing processor
J Tobin, A Breuer, A Heinecke, C Yount, Y Cui
International Supercomputing Conference, 139-157, 2017
142017
Genetic algorithm based auto-tuning of seismic applications on multi and manycore computers
C Andreolli, P Thierry, L Borges, C Yount, G Skinner
EAGE Workshop on High Performance Computing for Upstream, cp-426-00017, 2014
142014
Vector friendly instruction format and execution thereof
RC Valentine, JC San Adrian, RE Sans, RD Cavin, BL Toll, SG Duran, ...
US Patent 9,513,917, 2016
132016
Method to assess energy efficiency of HPC system operated with and without power constraints
D Bodas, M Arunachalam, I Sharapov, CR Yount, SB Huck, R Huggahalli, ...
US Patent 9,971,391, 2018
122018
Method and apparatus for generation of validation tests
CR Yount, MA Goveas
US Patent 6,931,629, 2005
112005
Optimised finite difference computation from symbolic equations
M Lange, N Kukreja, F Luporini, M Louboutin, C Yount, J Hückelheim, ...
arXiv preprint arXiv:1707.03776, 2017
102017
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