| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 770 | 2017 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 175 | 2016 |
| Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts JH Zhang, C Radens, SJ Bentley, BA Cohen, KY Lim US Patent 9,530,866, 2016 | 89 | 2016 |
| Vertical gate-all-around TFET JH Zhang US Patent 9,385,195, 2016 | 75 | 2016 |
| Preparation of AgBr quantum dots via electroporation of vesicles NM Correa, H Zhang, ZA Schelly Journal of the American Chemical Society 122 (27), 6432-6434, 2000 | 71 | 2000 |
| A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around nanosheet devices N Loubet, S Kal, C Alix, S Pancharatnam, H Zhou, C Durfee, M Belyansky, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.4. 1-11.4. 4, 2019 | 68 | 2019 |
| Stacked transistors with different channel widths K Cheng, LA Clevenger, BS Pranatharthiharan, J Zhang US Patent 9,660,028, 2017 | 65 | 2017 |
| Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019 | 64 | 2019 |
| Methods of forming replacement gate structures and bottom and top source drain regions on a vertical transistor device Steven J Bentley, John H. Zhang , Kwan-Yong Lim, Hiroaki Niimi TW Patent I613,735, 2018 | 62* | 2018 |
| Methods of forming replacement gate structures and bottom and top source drain regions on a vertical transistor device Steven J Bentley, John H. Zhang , Kwan-Yong Lim, Hiroaki Niimi TW Patent App. 201,743,383, 2017 | 62* | 2017 |
| Methods of forming replacement gate structures and bottom and top source drain regions on a vertical transistor device Steven J Bentley, John H. Zhang , Kwan-Yong Lim, Hiroaki Niimi US Patent 9,640,636, 2017 | 62 | 2017 |
| Self-aligned gate-first VFETs using a gate spacer recess JH Zhang, KY Lim, SJ Bentley, C Park US Patent 9,536,793, 2017 | 58 | 2017 |
| Theoretical Study of the Molecular and Electronic Structures of Neutral Silver Bromide Clusters (AgBr)n, n = 1−9 H Zhang, ZA Schelly, DS Marynick The Journal of Physical Chemistry A 104 (26), 6287-6294, 2000 | 57 | 2000 |
| Vertical tunneling FinFET Q Liu, JH Zhang US Patent 10,084,080, 2018 | 56 | 2018 |
| Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI J Zhang, S Bentley, KY Lim US Patent 9,773,708, 2017 | 53 | 2017 |
| Methods of forming vertical transistor devices with self-aligned replacement gate structures JH Zhang, C Radens, SJ Bentley, BA Cohen, KY Lim US Patent 9,530,863, 2016 | 48 | 2016 |
| DRAM interconnect structure having ferroelectric capacitors exhibiting negative capacitance JH Zhang US Patent 10,128,327, 2018 | 45 | 2018 |
| DRAM interconnect structure having ferroelectric capacitors exhibiting negative capacitance JH Zhang US Patent 10,128,327, 2018 | 45 | 2018 |
| Using backside passive elements for multilevel 3D wafers alignment applications JH Zhang, LA Clevenger, XU Yiheng US Patent 8,921,976, 2014 | 45 | 2014 |
| Copper interconnect structure having a graphene cap JH Zhang, C Goldberg, W Kleemeier, RK Sampson US Patent 8,476,765, 2013 | 45 | 2013 |
L.A. ClevengerIBM ResearchVerified email at us.ibm.com
