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Shaolan Li
Shaolan Li
Verified email at ece.gatech.edu - Homepage
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Year
A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure
S Li, B Qiao, M Gandara, DZ Pan, N Sun
IEEE Journal of Solid-State Circuits 53 (12), 3484-3496, 2018
1092018
A 174.3-dB FoM VCO-Based CT Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS
S Li, A Mukherjee, N Sun
IEEE Journal of Solid-State Circuits 52 (7), 1940-1952, 2017
802017
A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier
X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, S Li, ...
IEEE Journal of Solid-State Circuits 55 (12), 3248-3259, 2020
722020
Wellgan: Generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout
B Xu, Y Lin, X Tang, S Li, L Shen, N Sun, DZ Pan
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
712019
GeniusRoute: A new analog routing paradigm using generative neural network guidance
K Zhu, M Liu, Y Lin, B Xu, S Li, X Tang, N Sun, DZ Pan
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
692019
MAGICAL: Toward fully automated analog IC layout leveraging human and machine intelligence
B Xu, K Zhu, M Liu, Y Lin, S Li, X Tang, N Sun, DZ Pan
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
672019
A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer
J Liu, S Li, W Guo, G Wen, N Sun
IEEE Journal of Solid-State Circuits 54 (2), 428-440, 2018
652018
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- M Structure
W Zhao, S Li, B Xu, X Yang, X Tang, L Shen, N Lu, DZ Pan, N Sun
IEEE Journal of Solid-State Circuits 55 (3), 666-679, 2019
552019
Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
X Tang, J Liu, Y Shen, S Li, L Shen, A Sanyal, K Ragab, N Sun
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (6), 2249-2262, 2022
442022
MAGICAL: An open-source fully automated analog IC layout system from netlist to GDSII
H Chen, M Liu, B Xu, K Zhu, X Tang, S Li, Y Lin, N Sun, DZ Pan
IEEE Design & Test 38 (2), 19-26, 2020
442020
A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure
S Li, B Qiao, M Gandara, N Sun
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2018
412018
A scaling compatible, synthesis friendly VCO-based delta-sigma ADC design and synthesis methodology
B Xu, S Li, N Sun, DZ Pan
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
342017
Design of non-volatile capacitive crossbar array for in-memory computing
YC Luo, A Lu, J Hur, S Li, S Yu
2021 IEEE International Memory Workshop (IMW), 1-4, 2021
312021
18.2 a 16fJ/Conversion-step time-domain two-step Capacitance-to-Digital converter
X Tang, S Li, L Shen, W Zhao, X Yang, R Williams, J Liu, Z Tan, N Hall, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 296-297, 2019
312019
Hierarchical and analytical placement techniques for high-performance analog circuits
B Xu, S Li, X Xu, N Sun, DZ Pan
Proceedings of the 2017 ACM on International Symposium on Physical Design, 55-62, 2017
312017
A 13.8-ENOB fully dynamic third-order noise-shaping SAR ADC in a single-amplifier EF-CIFF structure with hardware-reusing kT/C noise cancellation
TH Wang, R Wu, V Gupta, X Tang, S Li
IEEE Journal of Solid-State Circuits 56 (12), 3668-3680, 2021
292021
Error-feedback mismatch error shaping for high-resolution data converters
J Liu, CK Hsu, X Tang, S Li, G Wen, N Sun
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (4), 1342-1354, 2018
292018
Device layer-aware analytical placement for analog circuits
B Xu, S Li, CW Pui, D Liu, L Shen, Y Lin, N Sun, DZ Pan
Proceedings of the 2019 International Symposium on Physical Design, 19-26, 2019
282019
A two-step ADC with a continuous-time SAR-based first stage
L Shen, Y Shen, Z Li, W Shi, X Tang, S Li, W Zhao, M Zhang, Z Zhu, N Sun
IEEE Journal of Solid-State Circuits 54 (12), 3375-3385, 2019
262019
A 0.029MM2 17-FJ/Conv.-Step CT ADC with 2nd-Order Noise-Shaping SAR Quantizer
J Liu, S Li, W Guo, G Wen, N Sun
2018 IEEE symposium on VLSI circuits, 201-202, 2018
262018
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