Zainalabedin Navabi
Zainalabedin Navabi
Professor of Electrical and Computer Engineering, University of Tehran
Verified email at - Homepage
Cited by
Cited by
VHDL: Analysis and modeling of digital systems
Z Navabi
McGraw-Hill, 1993
EDXY–A low cost congestion-aware routing algorithm for network-on-chips
P Lotfi-Kamran, AM Rahmani, M Daneshtalab, A Afzali-Kusha, Z Navabi
Journal of Systems Architecture 56 (7), 256-264, 2010
Evaluation of pseudo adaptive XY routing using an object oriented model for NOC
M Dehyadgari, M Nickray, A Afzali-Kusha, Z Navabi
2005 International Conference on Microelectronics, 5 pp., 2005
Digital system test and testable design
Z Navabi
Springer doi: https://doi. org/10.1007/978-1-4419-7548-5, 2011
Online NoC switch fault detection and diagnosis using a high level fault model
A Alaghi, N Karimi, M Sedghi, Z Navabi
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007
Embedded core design with FPGAs
Z Navabi
McGraw-Hill Professional, 2006
Digital design and implementation with field programmable devices
Z Navabi
Springer Science & Business Media, 2004
Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification: Register Transfer Level Synthesis, Testbench, and Verification
Z Navabi
McGraw Hill Professional, 2005
BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs
P Lotfi-Kamran, M Daneshtalab, C Lucas, Z Navabi
2008 Design, Automation and Test in Europe, 1408-1413, 2008
A concurrent testing method for NoC switches
M Hosseinabady, A Banaiyan, MN Bojnordi, Z Navabi
Proceedings of the Design Automation & Test in Europe Conference 1, 6 pp., 2006
An efficient BIST method for testing of embedded SRAMs
MH Tehranipour, Z Navabi, SM Fakhraie
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001
NoC hot spot minimization using antnet dynamic routing algorithm
M Daneshtalab, A Sobhani, A Afzali-Kusha, O Fatemi, Z Navabi
IEEE 17th International Conference on Application-specific Systems …, 2006
VHDL: modular design and synthesis of cores and systems
Z Navabi
McGraw-Hill, 2007
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies
M Ansari, H Afzali-Kusha, B Ebrahimi, Z Navabi, A Afzali-Kusha, ...
Integration 50, 91-106, 2015
Emotion on FPGA: Model driven approach
MR Jamali, A Arami, M Dehyadegari, C Lucas, Z Navabi
Expert Systems with Applications 36 (4), 7369-7378, 2009
Real-time embedded emotional controller
MR Jamali, M Dehyadegari, A Arami, C Lucas, Z Navabi
Neural Computing and Applications 19 (1), 13-19, 2010
Reliability in application specific mesh-based NoC architectures
F Refan, H Alemzadeh, S Safari, P Prinetto, Z Navabi
2008 14th IEEE International On-Line Testing Symposium, 207-212, 2008
Simultaneous reduction of dynamic and static power in scan structures
S Sharifi, J Jaffari, M Hosseinabady, A Afzali-Kusha, Z Navabi
Design, Automation and Test in Europe, 846-851, 2005
Using the inter-and intra-switch regularity in NoC switch testing
M Hosseinabady, A Dalirsani, Z Navabi
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
An analytical model for reliability evaluation of NoC architectures
A Dalirsani, M Hosseinabady, Z Navabi
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 49-56, 2007
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