| Embedded deterministic test points C Acero, D Feltham, Y Liu, E Moghaddam, N Mukherjee, M Patyra, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017 | 53 | 2017 |
| Embedded deterministic test points for compact cell-aware tests C Acero, D Feltham, F Hapke, E Moghaddam, N Mukherjee, ... 2015 IEEE International Test Conference (ITC), 1-8, 2015 | 34 | 2015 |
| Logic BIST with capture-per-clock hybrid test points E Moghaddam, N Mukherjee, J Rajski, J Solecki, J Tyszer, J Zawada IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 32 | 2018 |
| Test point insertion in hybrid test compression/LBIST architectures E Moghaddam, N Mukherjee, J Rajski, J Tyszer, J Zawada 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 28 | 2016 |
| Full-scan LBIST with capture-per-cycle hybrid test points S Milewski, N Mukherjee, J Rajski, J Solecki, J Tyszer, J Zawada 2017 IEEE International Test Conference (ITC), 1-9, 2017 | 19 | 2017 |
| Hardware protection via logic locking test points M Chen, E Moghaddam, N Mukherjee, J Rajski, J Tyszer, J Zawada IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 17 | 2018 |
| Design for low test pattern counts H Konuk, E Moghaddam, N Mukherjee, J Rajski, D Solanki, J Tyszer, ... Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 17 | 2015 |
| On new test points for compact cell-aware tests C Acero, D Feltham, M Patyra, F Hapke, E Moghaddam, N Mukherjee, ... IEEE Design & Test 33 (6), 7-14, 2016 | 14 | 2016 |
| On test points enhancing hardware security E Moghaddam, N Mukherjee, J Rajski, J Tyszer, J Zawada 2016 IEEE 25th Asian Test Symposium (ATS), 61-66, 2016 | 10 | 2016 |
| Test application time reduction using capture-per-cycle test points J Rajski, S Milewski, N Mukherjee, J Solecki, J Tyszer, J Zawada US Patent 10,509,072, 2019 | 6 | 2019 |
| Quality assurance in memory built-in self-test tools A Au, A Pogiel, J Rajski, P Sydow, J Tyszer, J Zawada 17th International Symposium on Design and Diagnostics of Electronic …, 2014 | 6 | 2014 |
| Efficient Test Compression Configuration Selection CS Ye, SX Zheng, FJ Tsai, C Wang, KJ Lee, WT Cheng, SM Reddy, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 4 | 2021 |
| On new class of test points and their applications J Rajski, J Tyszer, J Zawada 2018 IEEE International Test Conference (ITC), 1-9, 2018 | 4 | 2018 |
| Prediction of test pattern count and test data volume for scan architectures under different input channel configurations FJ Tsai, CS Ye, KJ Lee, SX Zheng, Y Huang, WT Cheng, SM Reddy, ... 2020 IEEE International Test Conference (ITC), 1-10, 2020 | 3 | 2020 |
| Test point insertion for low test pattern counts J Rajski, EK Moghaddam, N Mukherjee, J Tyszer, J Zawada US Patent 10,444,282, 2019 | 2 | 2019 |
| Test Challenges of Intel IA Cores U Shpiro, K Wee, KH Tsai, J Zawada, X Lin 2020 IEEE International Test Conference (ITC), 1-5, 2020 | | 2020 |
| Test point-enhanced hardware security J Rajski, N Mukherjee, EK Moghaddam, J Tyszer, J Zawada US Patent 10,361,873, 2019 | | 2019 |
| On new class of test points and their applications J Zawada | | 2017 |
