| An 8-bit 1.8 V 500 MSPS CMOS segmented current steering DAC S Sarkar, S Banerjee 2009 IEEE Computer Society Annual Symposium on VLSI, 268-273, 2009 | 36 | 2009 |
| 500 MHz differential latched current comparator for calibration of current steering DAC S Sarkar, S Banerjee Proceedings of the 2014 IEEE Students' Technology Symposium, 309-312, 2014 | 21 | 2014 |
| An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture S Sarkar, R sankar Prasad, SK Dey, V Belde, S Banerjee 2008 IEEE International Symposium on Circuits and Systems, 149-152, 2008 | 18 | 2008 |
| A 10-Bit 500 MSPS segmented DAC with optimized current sources to avoid mismatch effect S Sarkar, S Banerjee 2015 IEEE Computer Society Annual Symposium on VLSI, 172-177, 2015 | 14 | 2015 |
| An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters S Sarkar, S Banerjee Microelectronics journal 45 (6), 666-677, 2014 | 13 | 2014 |
| A 10 bit 1 GSPS Nyquist DAC in 180 nm CMOS with high FOM S Sarkar, S Banerjee Analog Integrated Circuits and Signal Processing 80, 59-68, 2014 | 11 | 2014 |
| An IoT-Based Pollution Monitoring System Using Data Analytics Approach H Srivastava, S Mishra, SK Das, S Sarkar Electronic Systems and Intelligent Computing: Proceedings of ESIC 2020, 187-198, 2020 | 7 | 2020 |
| A 1.8 V 8-bit 500 MSPS segmented current steering DAC with> 66 dB SFDR S Samanta, S Sarkar 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 13-17, 2020 | 6 | 2020 |
| A 6-Bit 500 MSPS segmented current steering DAC with on-chip high precision current reference S Khandagale, S Sarkar 2016 International Conference on Computing, Communication and Automation …, 2016 | 6 | 2016 |
| Root growth and water use pattern of groundnut at varying soil water regimes S Sarkar, S Kar Proceeding of the National Symposium on Principles of Soil water …, 2000 | 5 | 2000 |
| A pairwise swap enabled randomized DEM addressing intersegment mismatch for current steering digital-to-analog converters S Samanta, S Sarkar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (9 …, 2022 | 4 | 2022 |
| A 10-bit 500 MSPS Segmented CS-DAC of> 77 dB SFDR upto the Nyquist with Hexa-decal biasing S Samanta, S Sarkar 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-4, 2020 | 3 | 2020 |
| A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation S Samanta, S Sarkar AEU-International Journal of Electronics and Communications 161, 154528, 2023 | 2 | 2023 |
| An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique S Khandagale, S Sarkar 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-2, 2016 | 2 | 2016 |
| Dual-Mode Conversion Gating, Comparator Merging, and Reference-Less Calibration for 2.7× Energy Reduction in SAR ADCs under Low-Activity Inputs K Ali, JH Teo, S Sarkar, M Alioto IEEE Solid-State Circuits Letters 6, 57-60, 2023 | 1 | 2023 |
| An IoT-Based Air Quality Monitoring with Deep Learning Model System H Srivastava, K Bansal, SK Das, S Sarkar Research in Intelligent and Computing in Engineering: Select Proceedings of …, 2021 | 1 | 2021 |
| An Efficient IoT Technology Cloud-Based Pollution Monitoring System H Srivastava, K Bansal, S Kumar Das, S Sarkar International Conference on Emerging Trends and Advances in Electrical …, 2020 | 1 | 2020 |
| A 10-bit 500 MSPS segmented DAC with distributed octal biasing scheme S Sarkar, S Banerjee 2015 International Conference on Signal Processing, Computing and Control …, 2015 | 1 | 2015 |
| Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique S Samanta, S Sarkar International Journal of Circuit Theory and Applications 52 (5), 2191-2204, 2024 | | 2024 |
| An 8-bit 100 kS/s Low Power SAR ADC with Modified EPC for Bio-Medical Applications D Kumaradasan, SK Kar, S Sarkar 2023 IEEE Silchar Subsection Conference (SILCON), 1-6, 2023 | | 2023 |
