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Charan Surisetty
Charan Surisetty
Verified email at us.ibm.com - Homepage
Title
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Cited by
Year
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ...
2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016
1742016
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
1082014
Tungsten and cobalt metallization: A material study for MOL local interconnects
V Kamineni, M Raymond, S Siddiqui, F Mont, S Tsai, C Niu, A Labonte, ...
2016 IEEE International Interconnect Technology Conference/Advanced …, 2016
572016
Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors
K Cheng, A Khakifirooz, A Reznicek, CV Surisetty
US Patent 9,059,164, 2015
562015
Air spacer for 10nm FinFET CMOS and beyond
K Cheng, C Park, C Yeung, S Nguyen, J Zhang, X Miao, M Wang, ...
2016 IEEE International Electron Devices Meeting (IEDM), 17.1. 1-17.1. 4, 2016
532016
Strained FinFET by epitaxial stressor independent of gate pitch
K Cheng, P Hashemi, A Khakifirooz, A Reznicek, CVVS Surisetty
US Patent 9,647,113, 2017
522017
Strained FinFET by epitaxial stressor independent of gate pitch
K Cheng, P Hashemi, A Khakifirooz, A Reznicek, CVVS Surisetty
US Patent 9,647,113, 2017
522017
Stable contact on one-sided gate tie-down structure
OK Injo, B Pranatharthiharan, SC Seo, CVVS Surisetty
US Patent 9,685,340, 2017
442017
Methods of forming replacement gate structures on semiconductor devices and the resulting device
R Xie, P Shom, C Jin, CVVS Surisetty
US Patent 8,772,101, 2014
442014
Bottom oxidation through STI (BOTS)—A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
K Cheng, S Seo, J Faltermeier, D Lu, T Standaert, I Ok, A Khakifirooz, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
352014
Cleaning solutions for ultrathin Co barriers for advanced technology nodes
SR Alety, URK Lagudu, R Popuri, R Patlolla, CVVS Surisetty, SV Babu
ECS Journal of Solid State Science and Technology 6 (9), P671, 2017
312017
Nanosheet isolation for bulk CMOS non-planar devices
B Pranatharthiharan, OK Injo, SC Seo, CVVS Surisetty
US Patent 9,871,099, 2018
282018
Method of forming contact useful in replacement metal gate processing and related semiconductor structure
B Pranatharthiharan, OK Injo, CVVS Surisetty
US Patent 9,337,094, 2016
272016
Dielectric cap layer for replacement gate with self-aligned contact
B Pranatharthiharan, CVVS Surisetty, J Wang, CS Park, R Xie
US Patent App. 13/672,864, 2014
262014
Semiconductor device replacement metal gate with gate cut last in RMG
AM Greene, BP Haran, OK Injo, CV Surisetty
US Patent 10,381,458, 2019
252019
Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures
N Breil, A Carr, T Kuratomi, C Lavoie, IC Chen, M Stolfi, KD Chiu, W Wang, ...
2017 Symposium on VLSI Technology, T216-T217, 2017
232017
Methods for replacing gate sidewall materials with a low-k spacer
K Cheng, A Khakifirooz, A Reznicek, CVVS Surisetty
US Patent 9,349,835, 2016
23*2016
Dissolution inhibition in Cu-CMP using dodecyl-benzene-sulfonic acid surfactant with oxalic acid and glycine as complexing agents
C Surisetty, PC Goonetilleke, D Roy, SV Babu
Journal of The Electrochemical Society 155 (12), H971, 2008
232008
Oxalic-acid-based slurries with tunable selectivity for copper and tantalum removal in CMP
S Janjam, C Surisetty, S Pandija, D Roy, SV Babu
Electrochemical and Solid-State Letters 11 (3), H66, 2008
232008
Borderless contacts for semiconductor transistors
K Cheng, A Khakifirooz, A Reznicek, R Sreenivasan, CV Surisetty, ...
US Patent 8,728,927, 2014
222014
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