| Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics C Batten, A Joshi, J Orcutt, A Khilo, B Moss, CW Holzwarth, MA Popovic, ... IEEE Micro 29 (4), 8-21, 2009 | 552 | 2009 |
| Silicon-photonic clos networks for global on-chip communication A Joshi, C Batten, YJ Kwon, S Beamer, I Shamim, K Asanovic, ... 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 124-133, 2009 | 428 | 2009 |
| Re-architecting DRAM memory systems with monolithically integrated silicon photonics S Beamer, C Sun, YJ Kwon, A Joshi, C Batten, V Stojanović, K Asanović ACM SIGARCH Computer Architecture News 38 (3), 129-140, 2010 | 147 | 2010 |
| Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM M Zangeneh, A Joshi Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 22 (8 …, 2014 | 120 | 2014 |
| Designing chip-level nanophotonic interconnection networks C Batten, A Joshi, V Stojanovć, K Asanović Integrated Optical Interconnect Architectures for Embedded Systems, 81-135, 2013 | 110 | 2013 |
| Hardware performance counters can detect malware: Myth or fact? B Zhou, A Gupta, R Jahanshahi, M Egele, A Joshi Asia Conference on Computer and Communications Security, 457-468, 2018 | 73 | 2018 |
| Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture C Chen, A Joshi Selected Topics in Quantum Electronics, IEEE Journal of 19 (2), 2013 | 67 | 2013 |
| Thermal management of manycore systems with silicon-photonic networks T Zhang, JL Abellán, A Joshi, AK Coskun Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 …, 2014 | 63 | 2014 |
| MGPUSim: Enabling Multi-GPU Performance Modeling and Optimization Y Sun, T Baruah, SA Mojumder, S Dong, X Gong, S Treadway, Y Bao, ... International Symposium on Computer Architecture (ISCA), 2019 | 56 | 2019 |
| Detecting hardware trojans using backside optical imaging of embedded watermarks B Zhou, R Adato, M Zangeneh, T Yang, A Uyar, B Goldberg, S Unlu, ... Proceedings of the 52nd Annual Design Automation Conference (DAC), 111, 2015 | 50 | 2015 |
| Asymmetric NoC Architectures for GPU Systems AKK Ziabari, JL Abellán, Y Ma, A Joshi, D Kaeli Network-on-chip Symposium (NOCS), 2015 | 43 | 2015 |
| Sharing and Placement of On-chip Laser Sources in Silicon-Photonic NoCs C Chen, T Zhang, P Contu, J Klamkin, AK Coskun, A Joshi International Symposium on Networks-on-Chip (NOCS), 2014 | 42 | 2014 |
| Reliable mlc nand flash memories based on nonlinear t-error-correcting codes Z Wang, M Karpovsky, A Joshi 2010 IEEE/IFIP International Conference on Dependable Systems & Networks …, 2010 | 40 | 2010 |
| BlackParrot: An agile open-source RISC-V multicore for accelerator SoCs D Petrisko, F Gilani, M Wyse, DC Jung, S Davidson, P Gao, C Zhao, ... IEEE Micro 40 (4), 93-102, 2020 | 39 | 2020 |
| Profiling DNN Workloads on a Volta-based DGX-1 System SA Mojumder, MS Louis, Y Sun, AK Ziabari, JL Abellán, J Kim, D Kaeli, ... IEEE International Symposium on Workload Characterization (IISWC), 2018 | 36 | 2018 |
| Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation JL Abellan, AK Coskun, A Gu, W Jin, A Joshi, AB Kahng, J Klamkin, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 35 | 2017 |
| Neural network-based accelerators for transcendental function approximation S Eldridge, F Raudies, D Zou, A Joshi Proceedings of the 24th edition of the great lakes symposium on VLSI, 169-174, 2014 | 35 | 2014 |
| UMH: A hardware-based unified memory hierarchy for systems with multiple discrete GPUs AK Ziabari, Y Sun, Y Ma, D Schaa, JL Abellán, R Ubal, J Kim, A Joshi, ... ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-25, 2016 | 33 | 2016 |
| Leveraging silicon-photonic NoC for designing scalable GPUs AKK Ziabari, JL Abellán, R Ubal, C Chen, A Joshi, D Kaeli Proceedings of the 29th ACM on International Conference on Supercomputing …, 2015 | 32 | 2015 |
| Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing AJ Joshi, GG Lopez, JA Davis IEEE transactions on very large scale integration (VLSI) systems 15 (9), 990 …, 2007 | 31 | 2007 |
Vladimir StojanovicProfessor of Electrical Engineering and Computer Sciences, University of CaliforniaVerified email at berkeley.edu
