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Sujit Dey
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Cited by
Year
Testing embedded-core-based system chips
Y Zorian, EJ Marinissen, S Dey
Computer 32 (6), 52-60, 1999
8181999
Testing embedded-core based system chips
Y Zorian, EJ Marinissen, S Dey
Test Conference, 1998. Proceedings., International, 130-143, 1998
8181998
Testing embedded-core based system chips
EJ Marinissen, S Dey
In Proceedings IEEE International Test Conference (ITC, 1998
818*1998
Battery-driven system design: A new frontier in low power design
K Lahiri, S Dey, D Panigrahi, A Raghunathan
Proceedings of the 2002 Asia and South Pacific Design Automation Conference, 261, 2002
5412002
An interconnect architecture for networking systems on chips
F Karim, A Nguyen, S Dey
Micro, IEEE 22 (5), 36-45, 2002
4352002
High-level power analysis and optimization
A Raghunathan, NK Jha, S Dey
Kluwer Academic Publishers, 1998
371*1998
Fault modeling and simulation for crosstalk in system-on-chip interconnects
M Cuviello, S Dey, X Bai, Y Zhao
Proceedings of the 1999 IEEE/ACM international conference on Computer-aided …, 1999
3331999
Video-Aware Scheduling and Caching in the Radio Access Network
H Ahlehagh, S Dey
IEEE, 0
302
Software-based self-testing methodology for processor cores
L Chen, S Dey
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2001
2972001
Battery Life Estimation of Mobile Embedded Systems
K Lahiri, S Dey, R Rao, D Panigrahi, C Chiasserini, A Raghunathan
281*2001
Battery life estimation of mobile embedded systems
T Panigrahi, D Panigrahi, C Chiasserini, S Dey, R Rao, A Raghunathan, ...
VLSI Design, 2001. Fourteenth International Conference on, 57-63, 2001
2812001
System-level performance analysis for designing on-chip communication architectures
K Lahiri, A Raghunathan, S Dey
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2001
2692001
Adaptive Mobile Cloud Computing to Enable Rich Mobile Multimedia Applications
S Wang, S Dey
IEEE, 2013
2612013
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
J Liou, A Krstic, L Wang, TKT Cheng, L Chen, WC Lai, SJ Dey, C Chang, ...
IEEE Design & Test of Computers 19 (4), 18-27, 2002
2162002
On-chip communication architecture for OC-768 network processors
F Karim, A Nguyen, S Dey, R Rao
Proceedings of the 38th annual Design Automation Conference, 678-683, 2001
2062001
On-Chip Communication Architecture for OC-768 Network Processors
S Dey, R Rao
206*2001
INTELLIGENT VIDEO SIGNAL ENCODING UTILIZING REGIONS OF INTEREST INFORMATION
J WEN, S DEY, P AROLE, J ZAN, S BHAT, A ILLIC
WO Patent 2,008,077,119, 2008
190*2008
Intelligent Video Signal Encoding Utilizing Regions of Interest Information
JG Wen, S Dey, P Arole, J Zan, S Bhat, A Illic
US Patent App. 11/960,385, 2007
190*2007
A scalable software-based self-test methodology for programmable processors
L Chen, S Ravi, A Raghunathan, S Dey
Proceedings of the 40th annual Design Automation Conference, 548-553, 2003
1882003
Digital content buffer for adaptive streaming
S Dey, D Wong, J Wen, Y Takebuchi, P Arole, D Panigrahi
US Patent 7,743,161, 2010
1862010
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