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Pareesa Ameneh Golnari
Pareesa Ameneh Golnari
Verified email at microsoft.com
Title
Cited by
Cited by
Year
Design and implementation of time and frequency synchronization in LTE
A Golnari, M Shabany, A Nezamalhosseini, G Gulak
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015
432015
A Low Complexity Architecture for the Cell Search Applied to the LTE Systems
A Golnari, G Sharifan, Y Amini, M Shabany
19th IEEE International Conference on Electronics, Circuits and Systems …, 2012
132012
Error-tolerant processors: Formal specification and verification
A Golnari, Y Vizel, S Malik
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 286-293, 2015
112015
Evaluating matrix representations for error-tolerant computing
PA Golnari, S Malik
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
42017
Sparse matrix to matrix multiplication: a representation and architecture for acceleration
S Malik, PA Golnari
2019 IEEE 30th International Conference on Application-specific Systems …, 2019
12019
Sparse matrix to matrix multiplication: A representation and architecture for acceleration (long version)
PA Golnari, S Malik
arXiv preprint arXiv:1906.00327, 2019
12019
PPU: A control error-tolerant processor for streaming applications with formal guarantees
PA Golnari, Y Yetim, M Martonosi, Y Vizel, S Malik
ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (3), 1-29, 2017
12017
Computing on Large, Sparse Datasets and Error-Prone Fabrics
PA Golnari
Princeton University, 2018
2018
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