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Alpa Trivedi
Alpa Trivedi
Senior Research Scientist, Intel Labs
Verified email at intel.com
Title
Cited by
Cited by
Year
Method and system for protecting memory information in a platform
ATN Trivedi, DM Durham, M Long, S Chhabra, UR Savagaonkar, ...
US Patent 9,092,644, 2015
82*2015
Trusted timer service
ATN Trivedi, S Chhabra, KS Grewal, DM Durham
US Patent 10,068,068, 2018
70*2018
Memory integrity with error detection and correction
DM Durham, S Chhabra, S Deutsch, M Long, ATN Trivedi
US Patent 9,990,249, 2018
512018
Creating secure channels between a protected execution environment and fixed-function endpoints
AN Trivedi, S Chhabra, U Savagaonkar, M Long
US Patent 9,852,301, 2017
43*2017
Encryption interface
EM Kishinevsky, UR Savagaonkar, ATN Trivedi, S Chhabra, BV Patel, ...
US Patent 9,614,666, 2017
332017
Parallelized counter tree walk for low overhead memory replay protection
S Chhabra, UR Savagaonkar, DM Durham, NL Cooray, M Long, ...
US Patent 8,819,455, 2014
322014
Entry/exit architecture for protected device modules
X Kang, ATN Trivedi, S Chhabra, P Dewan, UR Savagaonkar, ...
US Patent 9,652,609, 2017
252017
Secure environment for graphics processing units
P Dewan, UR Savagaonkar, DM Durham, PS Schmitz, J Martin, ...
US Patent 9,519,803, 2016
202016
Security plugin for a system-on-a-chip platform
MR Sastry, AN Trivedi, M Long
US Patent 10,726,162, 2020
192020
Techniques for compression memory coloring
DM Durham, S Deutsch, S Komijani, ATN Trivedi, S Chhabra
US Patent 10,387,305, 2019
182019
Apparatus, system and method of protecting domains of a multimode wireless radio transceiver
FA Sheikh, P Koeberl, J Walker, H Alavi, M Long, RK Krishnamurthy, ...
US Patent 9,307,409, 2016
172016
Enabling stateless accelerator designs shared across mutually-distrustful tenants
A Trivedi, C Rozas
US Patent 11,354,482, 2022
152022
Technologies for secure device configuration and management
R Lal, PM Pappachan, L Kida, K Zmudzinski, S Chhabra, A Basak, ...
US Patent 11,416,415, 2022
142022
Low-overhead cryptographic method and apparatus for providing memory confidentiality, integrity and replay protection
S Chhabra, UR Savagaonkar, CV Rozas, ATN Trivedi, M Long, ...
US Patent 9,053,346, 2015
142015
Article holder adapted for being supported by a fence
LC Roach
US Patent 6,659,412, 2003
142003
Entry/exit architecture for protected device modules
X Kang, ATN Trivedi, S Chhabra, P Dewan, UR Savagaonkar, ...
US Patent 9,087,202, 2015
132015
Enabling late-binding of security features via configuration security controller for accelerator devices
A Trivedi, S Schulz, P Koeberl
US Patent 11,763,043, 2023
122023
Broadcast remote sealing for scalable trusted execution environment provisioning
S Schulz, A Trivedi, P Koeberl
US Patent 11,328,111, 2022
122022
System, apparatus and method for secure monotonic counter operations in a processor
P Dewan, S Chhabra, DM Durham, KS Grewal, ATN Trivedi
US Patent 10,592,435, 2020
122020
Scalable runtime validation for on-device design rule checks
F Turan, P Koeberl, A Trivedi, S Schulz, S Weber
US Patent 11,556,677, 2023
112023
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