| Current conveyor-based square/triangular waveform generators with improved linearity D Pal, A Srinivasulu, BB Pal, A Demosthenous, BN Das IEEE Transactions on Instrumentation and Measurement 58 (7), 2174-2180, 2008 | 122 | 2008 |
| Very low-noise ENG amplifier system using CMOS technology R Rieger, M Schuettler, D Pal, C Clarke, P Langlois, J Taylor, ... IEEE Transactions on Neural Systems and Rehabilitation Engineering 14 (4 …, 2006 | 69 | 2006 |
| An energy efficient multilayer MAC protocol (ML MAC) for wireless sensor networks MK Jha, AK Pandey, D Pal, A Mohan Int. Jl. of Electronics & Communication 65, 209-216, 2011 | 64* | 2011 |
| Novel CMOS Multi-bit Counter for Speed- Power Optimization in Multiplier Design AGNDP Aloke Saha, Rahul Pal Int. J. Electron. Commun. (AEÜ) 95, 189–198, 2018 | 38* | 2018 |
| A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier C Sawigun, A Demosthenous, D Pal 2007 18th European Conference on Circuit Theory and Design, 751-754, 2007 | 33 | 2007 |
| Low‐power 6‐GHz wave‐pipelined 8b × 8b multiplier A Saha, D Pal, M Chandra IET Circuits, Devices & Systems 7 (3), 124-140, 2013 | 29 | 2013 |
| Thermal model of MOSFET with SELBOX structure MR Narayanan, H Al-Nashash, D Pal, M Chandra Journal of Computational Electronics 12, 803-811, 2013 | 27 | 2013 |
| DPL-based novel binary-to-ternary converter on CMOS technology ASD Pal Int. J. Electron. Commun. (AEÜ), 92, 69-73, 2018 | 25 | 2018 |
| Benchmarking of DPL-based 8b× 8b novel wave-pipelined multiplier A Saha, D Pal, M Chandra International Journal of Electronics Letters 5 (1), 115-128, 2017 | 21 | 2017 |
| Novel current-mode waveform generator with independent frequency and amplitude control D Pal, A Srinivasulu, M Goswami 2009 IEEE International Symposium on Circuits and Systems, 2946-2949, 2009 | 21 | 2009 |
| A low-power CMOS analog voltage buffer using compact adaptive biasing C Sawigun, J Mahattanakul, A Demosthenous, D Pal 2007 18th European Conference on Circuit Theory and Design, 1-4, 2007 | 21 | 2007 |
| DPL-based novel time equalized CMOS ternary-to-binary converter A Saha, D Pal International Journal of Electronics 107 (3), 431-443, 2020 | 20 | 2020 |
| Analysis of kink reduction in SOI MOSFET using selective back oxide structure M Narayanan, H Al-Nashash, B Mazhari, D Pal, M Chandra Active and Passive Electronic Components 2012 (1), 565827, 2012 | 20 | 2012 |
| DPL-based novel CMOS 1-trit ternary full-adder A Saha, RK Singh, P Gupta, D Pal International Journal of Electronics 108 (2), 218-236, 2021 | 16 | 2021 |
| Three novel single-stage full swing 3-input XOR ASDP P. Vijaya Lakshmi, S. Musala International Journal of Electronics, 2018 | 16 | 2018 |
| Design of low power, high speed, low offset and area efficient dynamic-latch comparator for SAR-ADC K Bandla, A Harikrishnan, D Pal 2020 International Conference on Innovative Trends in Communication and …, 2020 | 15 | 2020 |
| Efficient ternary comparator on CMOS technology A Saha, ND Singh, D Pal Microelectronics Journal 109, 105005, 2021 | 14 | 2021 |
| Novel, low-supply, differential XOR/ XNOR with rail-to-rail swing, for hamming-code generation ASDP M. Sarada International Journal of Electronics Letters 6 (3), 272-287, 2018 | 13 | 2018 |
| Novel high speed MCML 8-bit by 8-bit multiplier A Saha, D Pal, M Chandra, MK Goswami 2011 International Conference on Devices and Communications (ICDeCom), 1-5, 2011 | 13 | 2011 |
| Studies and minimization of kink effect in SOI MOSFET devices with SELBOX structure MR Narayanan, H Al-Nashash, B Mazhari, D Pal 2008 International Conference on Microelectronics, 232-235, 2008 | 12 | 2008 |
