Follow
Prof. Dipankar Pal
Prof. Dipankar Pal
Professor, Dept. of EEE and E&I, BITS-Pilani, Goa
Verified email at goa.bits-pilani.ac.in
Title
Cited by
Cited by
Year
Current conveyor-based square/triangular waveform generators with improved linearity
D Pal, A Srinivasulu, BB Pal, A Demosthenous, BN Das
IEEE Transactions on Instrumentation and Measurement 58 (7), 2174-2180, 2008
1212008
Very low-noise ENG amplifier system using CMOS technology
R Rieger, M Schuettler, D Pal, C Clarke, P Langlois, J Taylor, ...
IEEE Transactions on Neural Systems and Rehabilitation Engineering 14 (4†…, 2006
672006
An energy efficient multilayer MAC protocol (ML MAC) for wireless sensor networks
MK Jha, AK Pandey, D Pal, A Mohan
Int. Jl. of Electronics & Communication 65, 209-216, 2011
63*2011
Novel CMOS Multi-bit Counter for Speed- Power Optimization in Multiplier Design
AGNDP Aloke Saha, Rahul Pal
Int. J. Electron. Commun. (AE‹) 95, 189–198, 2018
35*2018
A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier
C Sawigun, A Demosthenous, D Pal
2007 18th European Conference on Circuit Theory and Design, 751-754, 2007
332007
Thermal model of MOSFET with SELBOX structure
MR Narayanan, H Al-Nashash, D Pal, M Chandra
Journal of Computational Electronics 12, 803-811, 2013
272013
Low‐power 6‐GHz wave‐pipelined 8b ◊ 8b multiplier
A Saha, D Pal, M Chandra
IET Circuits, Devices & Systems 7 (3), 124-140, 2013
252013
DPL-based novel binary-to-ternary converter on CMOS technology
ASD Pal
Int. J. Electron. Commun. (AE‹), 92, 69-73, 2018
212018
Novel current-mode waveform generator with independent frequency and amplitude control
D Pal, A Srinivasulu, M Goswami
2009 IEEE International Symposium on Circuits and Systems, 2946-2949, 2009
212009
A low-power CMOS analog voltage buffer using compact adaptive biasing
C Sawigun, J Mahattanakul, A Demosthenous, D Pal
2007 18th European Conference on Circuit Theory and Design, 1-4, 2007
202007
Benchmarking of DPL-based 8b◊ 8b novel wave-pipelined multiplier
A Saha, D Pal, M Chandra
International Journal of Electronics Letters 5 (1), 115-128, 2017
192017
Analysis of kink reduction in SOI MOSFET using selective back oxide structure
M Narayanan, H Al-Nashash, B Mazhari, D Pal, M Chandra
Active and Passive Electronic Components 2012, 2012
182012
DPL-based novel time equalized CMOS ternary-to-binary converter
A Saha, D Pal
International Journal of Electronics 107 (3), 431-443, 2020
152020
Three novel single-stage full swing 3-input XOR
ASDP P. Vijaya Lakshmi, S. Musala
International Journal of Electronics, 2018
152018
Novel, low-supply, differential XOR/ XNOR with rail-to-rail swing, for hamming-code generation
ASDP M. Sarada
International Journal of Electronics Letters 6 (3), 272-287, 2018
142018
DPL-based novel CMOS 1-trit ternary full-adder
A Saha, RK Singh, P Gupta, D Pal
International Journal of Electronics 108 (2), 218-236, 2021
132021
Design of low power, high speed, low offset and area efficient dynamic-latch comparator for SAR-ADC
K Bandla, A Harikrishnan, D Pal
2020 International Conference on Innovative Trends in Communication and†…, 2020
132020
Novel high speed MCML 8-bit by 8-bit multiplier
A Saha, D Pal, M Chandra, MK Goswami
2011 International Conference on Devices and Communications (ICDeCom), 1-5, 2011
132011
Studies and minimization of kink effect in SOI MOSFET devices with SELBOX structure
MR Narayanan, H Al-Nashash, B Mazhari, D Pal
2008 International Conference on Microelectronics, 232-235, 2008
132008
Efficient ternary comparator on CMOS technology
A Saha, ND Singh, D Pal
Microelectronics Journal 109, 105005, 2021
112021
The system can't perform the operation now. Try again later.
Articles 1–20