Follow
Adam Izraelevitz
Title
Cited by
Cited by
Year
The rocket chip generator
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016
4782016
Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
A Izraelevitz, J Koenig, P Li, R Lin, A Wang, A Magyar, D Kim, C Schmidt, ...
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 209-216, 2017
1172017
Flicker: A dynamically adaptive architecture for power limited multicore systems
P Petrica, AM Izraelevitz, DH Albonesi, CA Shoemaker
Proceedings of the 40th Annual International Symposium on Computer …, 2013
1102013
The rocket chip generator. EECS Department
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17 4, 2016
802016
Specification for the FIRRTL Language
PS Li, AM Izraelevitz, J Bachrach
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-9, 2016
452016
Strober: Fast and accurate sample-based energy simulation for arbitrary RTL
D Kim, A Izraelevitz, C Celio, H Kim, B Zimmer, Y Lee, J Bachrach, ...
2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture …, 2016
412016
ACED: A hardware library for generating DSP systems
A Wang, P Rigge, A Izraelevitz, C Markley, J Bachrach, B Nikolić
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
132018
A methodology for reusable physical design
E Wang, C Schmidt, A Izraelevitz, J Wright, B Nikolić, E Alon, J Bachrach
2020 21st International Symposium on Quality Electronic Design (ISQED), 243-249, 2020
72020
A fast parameterized sha3 accelerator
C Schmidt, A Izraelevitz
tech. rep., 2015
72015
Illustrating the use of statistical experimental design and analysis for multiresponse prediction and optimization
AM Izraelevitz, CM Anderson-Cook, MS Hamada
Quality Engineering 23 (3), 265-277, 2011
72011
A mixed-signal risc-v signal analysis soc generator with a 16-nm finfet instance
S Bailey, P Rigge, J Han, R Lin, EY Chang, H Mao, Z Wang, C Markley, ...
IEEE Journal of Solid-State Circuits 54 (10), 2786-2801, 2019
62019
Unlocking Design Reuse with Hardware Compiler Frameworks
A Izraelevitz
University of California, Berkeley, 2019
42019
A generated multirate signal analysis RISC-V SoC in 16nm FinFET
S Bailey, J Han, P Rigge, R Lin, E Chang, H Mao, Z Wang, C Markley, ...
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 285-288, 2018
42018
Hammer: Enabling reusable physical design
E Wang, A Izraelevitz, C Schmidt, B Nikolic, E Alon, J Bachrach
Workshop on Open-Source EDA Technology (WOSET), 2018
42018
MLIR as hardware compiler infrastructure
S Eldridge, P Barua, A Chapyzhenka, A Izraelevitz, J Koenig, C Lattner, ...
Workshop on Open-Source EDA Technology (WOSET), 2021
32021
Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency
P Petrica, AM Izraelevitz, DH Albonesi, CA Shoemaker
US Patent 10,088,891, 2018
2018
Том. 2017-November. 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017.-Сер. 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017
X Wang, Y Yan, J He, S Yang, SXD Tan, C Cook, A Izraelevitz, J Koenig, ...
SAT 659, 666, 2017
2017
Advanced Parameterization Manual
A Izraelevitz
2014
Improving Hardware Reusability: Software Defined Hardware
A Izraelevitz, J Koenig, R Lin, C Markley, J Lawson, C Celio, C Schmidt, ...
The system can't perform the operation now. Try again later.
Articles 1–19