| Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond CC Liu, E Franke, Y Mignot, R Xie, CW Yeung, J Zhang, C Chi, C Zhang, ... Nature Electronics 1 (10), 562-569, 2018 | 102 | 2018 |
| III--V Junctionless Gate-All-Around Nanowire MOSFETs for High Linearity Low Power Applications Y Song, C Zhang, R Dowdy, K Chabak, PK Mohseni, W Choi, X Li IEEE Electron Device Letters 35 (3), 324-326, 2014 | 84 | 2014 |
| Channel geometry impact and narrow sheet effect of stacked nanosheet CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ... 2018 IEEE international electron devices meeting (IEDM), 28.6. 1-28.6. 4, 2018 | 76 | 2018 |
| Site-controlled VLS growth of planar nanowires: Yield and mechanism C Zhang, X Miao, PK Mohseni, W Choi, X Li Nano letters 14 (12), 6836-6841, 2014 | 73 | 2014 |
| III-V Nanowire Transistors for Low-Power Logic Applications: A Review and Outlook C Zhang, X Li IEEE Transaction on Electron Devices 63 (1), 223-234, 2016 | 72 | 2016 |
| High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth X Miao, K Chabak, C Zhang, P K. Mohseni, D Walker Jr, X Li Nano Letters 15 (5), 2780-2786, 2015 | 68 | 2015 |
| Gate length controlled vertical FETs K Cheng, X Miao, XU Wenyu, C Zhang US Patent 10,153,367, 2018 | 60 | 2018 |
| High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor J Zhang, T Ando, CW Yeung, M Wang, O Kwon, R Galatage, R Chao, ... 2017 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2017 | 58 | 2017 |
| Sub- -cm2 n-Type Contact Resistivity for FinFET Technology H Niimi, Z Liu, O Gluschenkov, S Mochizuki, J Fronheiser, J Li, ... IEEE Electron Device Letters 37 (11), 1371-1374, 2016 | 56 | 2016 |
| Transfer-printing of tunable porous silicon microcavities with embedded emitters H Ning, NA Krueger, X Sheng, H Keum, C Zhang, KD Choquette, X Li, ... Acs Photonics 1 (11), 1144-1150, 2014 | 55 | 2014 |
| Device architectures for enhanced photon recycling in thin‐film multijunction solar cells X Sheng, MH Yun, C Zhang, AM Al‐Okaily, M Masouraki, L Shen, S Wang, ... Advanced Energy Materials 5 (1), 1400919, 2015 | 49 | 2015 |
| Quenched phonon drag in silicon nanowires reveals significant effect in the bulk at room temperature J Sadhu, H Tian, J Ma, B Azeredo, J Kim, K Balasundaram, C Zhang, X Li, ... Nano letters 15 (5), 3159-3165, 2015 | 47 | 2015 |
| Monolithic barrier-all-around high electron mobility transistor with planar GaAs nanowire channel X Miao, C Zhang, X Li Nano letters 13 (6), 2548-2552, 2013 | 43 | 2013 |
| Fabrication of a vertical transistor with self-aligned bottom source/drain K Cheng, X Miao, XU Wenyu, C Zhang US Patent 10,083,871, 2018 | 41 | 2018 |
| FinFET performance with Si: P and Ge: Group-III-Metal metastable contact trench alloys O Gluschenkov, Z Liu, H Niimi, S Mochizuki, J Fronheiser, X Miao, J Li, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.2. 1-17.2. 4, 2016 | 39 | 2016 |
| Transistor with air spacer and self-aligned contact K Cheng, X Miao, P Xu, C Zhang US Patent 9,721,897, 2017 | 34 | 2017 |
| Vertical field effect transistor having U-shaped top spacer K Cheng, X Miao, XU Wenyu, C Zhang US Patent 9,859,166, 2018 | 33 | 2018 |
| A review of III–V planar nanowire arrays: selective lateral VLS epitaxy and 3D transistors C Zhang, X Miao, KD Chabak, X Li Journal of Physics D: Applied Physics 50 (39), 393001, 2017 | 33 | 2017 |
| Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain K Cheng, X Miao, XU Wenyu, C Zhang US Patent 9,899,515, 2018 | 32 | 2018 |
| Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices H Jagannathan, B Anderson, CW Sohn, G Tsutsui, J Strane, R Xie, S Fan, ... 2021 IEEE International Electron Devices Meeting (IEDM), 26.1. 1-26.1. 4, 2021 | 30 | 2021 |
Xin MiaoIBM ResearchVerified email at us.ibm.com
