| AlphaSyn: Logic synthesis optimization with efficient monte carlo tree search Z Pei, F Liu, Z He, G Chen, H Zheng, K Zhu, B Yu 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | 3 | 2023 |
| Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement S Liu, Z Wang, F Liu, Y Lin, B Yu, M Wong 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 3 | 2023 |
| CBTune: Contextual Bandit Tuning for Logic Synthesis F Liu, Z Pei, Z Yu, H Zheng, Z He, T Chen, B Yu | | 2024 |
| Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells Y Zhang, Y Pu, F Liu, P Liao, KY Chao, K Zhu, Y Lin, B Yu Proceedings of the 2024 International Symposium on Physical Design, 161-168, 2024 | | 2024 |
| LSTP: A Logic Synthesis Timing Predictor H Zheng, Z He, F Liu, Z Pei, B Yu | | 2024 |
