| Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock S Das, C Karfa, S Biswas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4 …, 2020 | 14 | 2020 |
| xMAS based accurate modeling and progress verification of NoCs S Das, C Karfa, S Biswas International Symposium on VLSI Design and Test, 792-804, 2017 | 5 | 2017 |
| Formal Modeling and Verification of Starvation Freedom in NoCs S Das, C Karfa Artificial Intelligence Driven Circuits and Systems: Select Proceedings of …, 2022 | 2 | 2022 |
| Deadlock avoidance in torus noc applying controlled move via wraparound channels S Das, C Karfa Artificial Intelligence Driven Circuits and Systems: Select Proceedings of …, 2022 | 2 | 2022 |
| Accelerating NoC Verification Using a Complete Model and Active Window S Das, C Karfa, S Biswas IEEE Access 10, 88985-88999, 2022 | 1 | 2022 |
| Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC S Das, C Karfa IEEE Embedded Systems Letters 14 (2), 67-70, 2021 | | 2021 |
| Tag only storage for capacity optimised last level cache in chip multiprocessors S Das, S Das, HK Kapoor 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-6, 2016 | | 2016 |
