BEOL vertical fuse formed over air gap MA Bergendahl, JJ Demarest, CJ Penny, CJ Waskiewicz US Patent 9,666,528, 2017 | 317 | 2017 |
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 175 | 2016 |
A 0.063 µm2FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch VS Basker, T Standaert, H Kawasaki, CC Yeh, K Maitra, T Yamashita, ... 2010 Symposium on VLSI Technology, 19-20, 2010 | 118 | 2010 |
22 nm technology compatible fully functional 0.1 μm26T-SRAM cell BS Haran, A Kumar, L Adam, J Chang, V Basker, S Kanakasabapathy, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 96 | 2008 |
Sub-25nm FinFET with advanced fin formation and short channel effect engineering T Yamashita, VS Basker, T Standaert, CC Yeh, T Yamamoto, K Maitra, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 14-15, 2011 | 77 | 2011 |
Nanometer-scale arrangement of human serum albumin by adsorption on defect arrays created with a finely focused ion beam AA Bergman, J Buijs, J Herbig, DT Mathes, JJ Demarest, CD Wilson, ... Langmuir 14 (24), 6785-6788, 1998 | 77 | 1998 |
Impact of back bias on ultra-thin body and BOX (UTBB) devices Q Liu, F Monsieur, A Kumar, T Yamamoto, A Yagishita, P Kulkarni, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 160-161, 2011 | 73 | 2011 |
FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 65 | 2016 |
Fully on-chip MAC at 14 nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format P Narayanan, S Ambrogio, A Okazaki, K Hosokawa, H Tsai, A Nomura, ... IEEE Transactions on Electron Devices 68 (12), 6629-6636, 2021 | 64 | 2021 |
UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below L Grenouillet, M Vinet, J Gimbert, B Giraud, JP Noel, Q Liu, P Khare, ... 2012 International Electron Devices Meeting, 3.6. 1-3.6. 4, 2012 | 62 | 2012 |
Sub- -cm2 n-Type Contact Resistivity for FinFET Technology H Niimi, Z Liu, O Gluschenkov, S Mochizuki, J Fronheiser, J Li, ... IEEE Electron Device Letters 37 (11), 1371-1374, 2016 | 56 | 2016 |
The effect of metal area and line spacing on TDDB characteristics of 45nm low-k SiCOH dielectrics F Chen, P McLaughlin, J Gambino, E Wu, J Demarest, D Meatyard, ... 2007 IEEE International Reliability Physics Symposium Proceedings. 45th …, 2007 | 49 | 2007 |
Investigation of CVD SiCOH low-k time-dependent dielectric breakdown at 65nm node technology F Chen, K Chanda, J Gill, M Angyal, J Demarest, T Sullivan, R Kontra, ... 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings …, 2005 | 49 | 2005 |
A 14 nm embedded stt-mram cmos technology D Edelstein, M Rizzolo, D Sil, A Dutta, J DeBrosse, M Wordeman, A Arceo, ... 2020 IEEE International Electron Devices Meeting (IEDM), 11.5. 1-11.5. 4, 2020 | 45 | 2020 |
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, B Haran, A Kumar, T Adam, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 128-129, 2011 | 45 | 2011 |
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL D Edelstein, H Rathore, C Davis, L Clevenger, A Cowley, T Nogami, ... 2004 IEEE International Reliability Physics Symposium. Proceedings, 316-319, 2004 | 43 | 2004 |
Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer LA Clevenger, SR Chiras, T Dalton, JJ Demarest, DN Dunn, ... US Patent 7,102,232, 2006 | 42 | 2006 |
Parasitic resistance reduction strategies for advanced CMOS FinFETs beyond 7nm H Wu, O Gluschenkov, G Tsutsui, C Niu, K Brew, C Durfee, C Prindle, ... 2018 IEEE International Electron Devices Meeting (IEDM), 35.4. 1-35.4. 4, 2018 | 40 | 2018 |
FinFET performance with Si: P and Ge: Group-III-Metal metastable contact trench alloys O Gluschenkov, Z Liu, H Niimi, S Mochizuki, J Fronheiser, X Miao, J Li, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.2. 1-17.2. 4, 2016 | 39 | 2016 |
Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node BD Briggs, CB Peethala, DL Rath, J Lee, S Nguyen, NV LiCausi, ... 2017 IEEE International Electron Devices Meeting (IEDM), 14.2. 1-14.2. 4, 2017 | 38 | 2017 |