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Cited by
Cited by
Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI
F Assaderaghi, D Sinitsky, SA Parke, J Bokor, PK Ko, C Hu
IEEE Transactions on Electron Devices 44 (3), 414-422, 1997
Mixed memory integration with NVRAM, DRAM and SRAM cell structures on same substrate
F Assaderaghi, LLC Hsu, JA Mandelman
US Patent 6,424,011, 2002
SOI FET design to reduce transient bipolar current
MMA Pelella, F Assaderaghi, LF Wagner Jr
US Patent 5,770,881, 1998
Two-device memory cell on SOI for merged logic and memory applications
F Assaderaghi, B Davari, LL Hsu, JA Mandelman, GG Shahidi
US Patent 5,784,311, 1998
Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure
LLC Hsu, JA Mandelman, F Assaderaghi
US Patent 6,232,173, 2001
T-Ram array having a planar cell structure and method for fabricating the same
LL Hsu, RV Joshi, F Assaderaghi
US Patent 6,552,398, 2003
Method and system for improving the performance on SOI memory arrays in an SRAM architecture system
LL Hsu, RV Joshi, F Assaderaghi, MJ Saccamango
US Patent 6,549,450, 2003
Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET
C Wann, F Assaderaghi, R Dennard, C Hu, G Shahidi, Y Taur
International Electron Devices Meeting. Technical Digest, 113-116, 1996
Double SOI device with recess etch and epitaxy
F Assaderaghi, TC Chen, KP Muller, EJ Nowak, DK Sadana, GG Shahidi
US Patent 6,432,754, 2002
Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications
F Assaderaghi, LLC Hsu, JA Mandelman, GG Shahidi, SH Voldman
US Patent 5,811,857, 1998
Dispensing device
PT Price, S Bley, B Sams
US Patent 6,770,056, 2004
The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta
J Chen, F Assaderaghi, PK Ko, C Hu
IEEE Electron Device Letters 13 (11), 572-574, 1992
Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure
LLC Hsu, JA Mandelman, F Assaderaghi
US Patent 5,880,991, 1999
Partially-depleted SOI technology for digital logic
GG Shahidi, A Ajmera, F Assaderaghi, RJ Bolam, E Leobandung, ...
1999 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1999
Integrated circuit with built-in heating circuitry to reverse operational degeneration
G Bronner, BS Haukness, F Assaderaghi, MD Kellam, M Horowitz
US Patent App. 12/516,499, 2010
T-RAM array having a planar cell structure and method for fabricating the same
LL Hsu, RV Joshi, F Assaderaghi, D Moy, W Rausch, J Culp
US Patent 6,713,791, 2004
Body contact MOSFET
A Bryant, PE Cottrell, JJ Ellis-Monaghan, RJ Gauthier Jr, EJ Nowak, ...
US Patent 6,677,645, 2004
A 16 Gb/s/link, 64 GB/s bidirectional asymmetric memory interface
H Lee, KYK Chang, JH Chun, T Wu, Y Frans, B Leibowitz, N Nguyen, ...
IEEE Journal of Solid-State Circuits 44 (4), 1235-1247, 2009
Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation
F Assaderaghi, LLC Hsu, JA Mandelman
US Patent 6,121,661, 2000
Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance
M Chan, F Assaderaghi, SA Parke, C Hu, PK Ko
IEEE electron device letters 15 (1), 22-24, 1994
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