Jianfeng Luo
Jianfeng Luo
Technical Director, Synopsys, Mountain View, CA, USA
Verified email at synopsys.com
Title
Cited by
Cited by
Year
Material removal mechanism in chemical mechanical polishing: theory and modeling
J Luo, DA Dornfeld
IEEE transactions on semiconductor manufacturing 14 (2), 112-133, 2001
7142001
Dummy filling technique for improved planarization of chip surface topography
S Sinha, J Luo, CC Chiang
US Patent 7,509,622, 2009
2382009
Analysis of two-dimensional thin structures (from micro-to nano-scales) using the boundary element method
JF Luo, YJ Liu, EJ Berger
Computational Mechanics 22 (5), 404-412, 1998
1781998
Effects of abrasive size distribution in chemical mechanical planarization: modeling and verification
J Luo, DA Dornfeld
IEEE Transactions on Semiconductor Manufacturing 16 (3), 469-476, 2003
1682003
Modeling of interphases in fiber-reinforced composites under transverse loading using the boundary element method
YJ Liu, N Xu, JF Luo
J. Appl. Mech. 67 (1), 41-49, 2000
1282000
Material removal regions in chemical mechanical planarization for submicron integrated circuit fabrication: coupling effects of slurry chemicals, abrasive size distribution …
J Luo, DA Dornfeld
IEEE Transactions on Semiconductor Manufacturing 16 (1), 45-56, 2003
1172003
Simulating topography of a conductive material in a semiconductor wafer
J Luo, Q Su, C Chiang
US Patent 7,289,933, 2007
962007
Interfacial stress analysis for multi-coating systems using an advanced boundary element method
JF Luo, YJ Liu, EJ Berger
Computational Mechanics 24 (6), 448-455, 2000
952000
Integrated modeling of chemical mechanical planarization for sub-micron IC fabrication: from particle scale to feature, die and wafer scales
J Luo, DA Dornfeld
Springer Science & Business Media, 2004
932004
A comparative study of double-gate and surroundinggate MOSFETs in strong inversion and accumulation using an analytical model
Y Chen, J Luo
Integration 1 (2), 6, 2001
682001
A layout dependent full-chip copper electroplating topography model
J Luo, Q Su, C Chiang, J Kawa
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
432005
An IC manufacturing yield model considering intra-die variations
J Luo, S Sinha, Q Su, J Kawa, C Chiang
Proceedings of the 43rd annual Design Automation Conference, 749-754, 2006
402006
Model based layout pattern dependent metal filling algorithm for improved chip surface uniformity in the copper process
S Sinha, J Luo, C Chiang
2007 Asia and South Pacific Design Automation Conference, 1-6, 2007
322007
Optimization of CMP from the Viewpoint of Consumable Effects
J Luo, DA Dornfeld
Journal of The Electrochemical Society 150 (12), G807, 2003
312003
Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
J Luo, S Sinha, Q Su, CC Chiang
US Patent 8,000,826, 2011
212011
Integrated modeling of chemical mechanical planarization/polishing (CMP) for integrated circuit fabrication: from particle scale to die and wafer scales
J Luo
University of California, Berkeley, 2003
172003
Integrated model for chemical-mechanical polishing based on a comprehensive material removal model
J Luo, DA Dornfeld, Z Mao, E Hwang
Sixth International Conference on Chemical-Mechanical Polish (CMP …, 2001
142001
Semiconductor Manufacturing
J Luo, DA Dornfeld
IEEE Transactions on 14 (2), 2001
142001
Impact of modern process technologies on the electrical parameters of interconnects
D Sinha, J Luo, S Rajagopalan, S Batterywala, NV Shenoy, H Zhou
20th International Conference on VLSI Design held jointly with 6th …, 2007
132007
Preventing double patterning odd cycles
J Luo
US Patent App. US20150026651 A1, 2015
102015
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