| Efficient hardware realization of convolutional neural networks using intra-kernel regular pruning M Yang, M Faraj, A Hussein, V Gaudet 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 180-185, 2018 | 18 | 2018 |
| A 16-bit high-speed low-power hybrid adder A Hussein, V Gaudet, H Mostafa, M Elmasry 2016 28th International Conference on Microelectronics (ICM), 313-316, 2016 | 7 | 2016 |
| A 4-bit 6GS/s time-based analog-to-digital converter AS Hussein, M Fawzy, MW Ismail, M Refky, H Mostafa 2014 26th International Conference on Microelectronics (ICM), 92-95, 2014 | 7 | 2014 |
| On the fault tolerance of stochastic decoders A Hussein, M Elmasry, V Gaudet 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 219-223, 2017 | 4 | 2017 |
| Modulation scheme for high order constellation ASM Hussein, VC Gaudet, P Mitran, M Jian US Patent 11,196,598, 2021 | | 2021 |
| Fault Tolerance of Stochastic Decoders for Error Correcting Codes A Hussein University of Waterloo, 2017 | | 2017 |
Vincent GaudetUniversity of WaterlooVerified email at uwaterloo.ca
