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Mark D. Hill
Mark D. Hill
Microsoft Partner Hardware Architect & University of Wisconsin-Madison Professor Emeritus
Verified email at cs.wisc.edu - Homepage
Title
Cited by
Cited by
Year
The gem5 simulator
N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ...
ACM SIGARCH computer architecture news 39 (2), 1-7, 2011
51722011
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
MMK Martin, DJ Sorin, BM Beckmann, MR Marty, M Xu, AR Alameldeen, ...
ACM SIGARCH Computer Architecture News 33 (4), 92-99, 2005
20492005
Amdahl's law in the multicore era
MD Hill, MR Marty
Computer 41 (7), 33-38, 2008
18202008
Weak ordering—a new definition
SV Adve, MD Hill
ACM SIGARCH Computer Architecture News 18 (2SI), 2-14, 1990
9731990
LogTM: Log-based transactional memory
KE Moore, J Bobba, MJ Moravan, MD Hill, DA Wood
The Twelfth International Symposium on High-Performance Computer …, 2006
9492006
Evaluating associativity in CPU caches
MD Hill, AJ Smith
IEEE Transactions on Computers 38 (12), 1612-1630, 1989
8481989
DBMSs on a modern processor: Where does time go?
A Ailamaki, DJ DeWitt, MD Hill, DA Wood
VLDB'99, Proceedings of 25th International Conference on Very Large Data …, 1999
7261999
Weaving Relations for Cache Performance.
A Ailamaki, DJ DeWitt, MD Hill, M Skounakis
VLDB 1, 169-180, 2001
5392001
A" flight data recorder" for enabling full-system multiprocessor deterministic replay
M Xu, R Bodik, MD Hill
Proceedings of the 30th annual international symposium on Computer …, 2003
5082003
The wisconsin wind tunnel: Virtual prototyping of parallel computers
SK Reinhardt, MD Hill, JR Larus, AR Lebeck, JC Lewis, DA Wood
Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and …, 1993
5071993
A primer on memory consistency and cache coherence
DJ Sorin, MD Hill, DA Wood
Synthesis lectures on computer architecture 6 (3), 1-212, 2011
4832011
Cache-conscious structure layout
TM Chilimbi, MD Hill, JR Larus
Proceedings of the ACM SIGPLAN 1999 conference on Programming language …, 1999
4831999
LogTM-SE: Decoupling hardware transactional memory from caches
L Yen, J Bobba, MR Marty, KE Moore, H Volos, MD Hill, MM Swift, ...
2007 IEEE 13th International Symposium on High Performance Computer …, 2007
4542007
SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery
DJ Sorin, MMK Martin, MD Hill, DA Wood
Proceedings 29th Annual International Symposium on Computer Architecture …, 2002
4112002
Token coherence: Decoupling performance and correctness
MMK Martin, MD Hill, DA Wood
ACM SIGARCH Computer Architecture News 31 (2), 182-193, 2003
3772003
Page placement algorithms for large real-indexed caches
RE Kessler, MD Hill
ACM Transactions on Computer Systems (TOCS) 10 (4), 338-359, 1992
3671992
Aspects of cache memory and instruction buffer performance
MD Hill
University of California, Berkeley, 1987
3581987
Efficient virtual memory for big memory servers
A Basu, J Gandhi, J Chang, MD Hill, MM Swift
ACM SIGARCH Computer Architecture News 41 (3), 237-248, 2013
3452013
Why on-chip cache coherence is here to stay
MMK Martin, MD Hill, DJ Sorin
Communications of the ACM 55 (7), 78-89, 2012
3432012
A unified formalization of four shared-memory models
SV Adve, MD Hill
IEEE Transactions on Parallel and distributed systems 4 (6), 613-624, 1993
3291993
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