Hadi Rasouli
Hadi Rasouli
Staff engineer, Qualcomm
Verified email at qti.qualcomm.com
Cited by
Cited by
Low-power single-and double-edge-triggered flip-flops for high-speed applications
SH Rasouli, A Khademzadeh, A Afzali-Kusha, M Nourani
IEE Proceedings-Circuits, Devices and Systems 152 (2), 118-122, 2005
Design optimization of FinFET domino logic considering the width quantization property
SH Rasouli, HF Dadgour, K Endo, H Koike, K Banerjee
IEEE Transactions on Electron Devices 57 (11), 2934-2943, 2010
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization
SH Rasouli, K Endo, K Banerjee
2009 IEEE/ACM International Conference on Computer-Aided Design-Digest of …, 2009
Double edge triggered feedback flip-flop in sub 100nm technology
SH Rasouli, A Amirabadi, A Seyedi, A Afzali-Kusha
Asia and South Pacific Conference on Design Automation, 2006., 6 pp., 2006
Grain-orientation induced quantum confinement variation in FinFETs and multi-gate ultra-thin body CMOS devices and implications for digital design
SH Rasouli, K Endo, JF Chen, N Singh, K Banerjee
IEEE transactions on electron devices 58 (8), 2282-2292, 2011
High-speed low-power FinFET based domino logic
SH Rasouli, H Koike, K Banerjee
2009 Asia and South Pacific Design Automation Conference, 829-834, 2009
Layout construction for addressing electromigration
SH Rasouli, A Datta, O Kwon
US Patent 9,786,663, 2017
A physical model for work-function variation in ultra-short channel metal-gate MOSFETs
SH Rasouli, C Xu, N Singh, K Banerjee
IEEE electron device letters 32 (11), 1507-1509, 2011
High performance standard cell with continuous oxide definition and characterized leakage current
X Chen, O Kwon, F Vang, A Datta, SH Rasouli
US Patent 9,318,476, 2016
Clock gated static pulsed flip-flop (CGSPFF) in sub 100 nm technology
AS Seyedi, SH Rasouli, A Amirabadi, A Afzali-Kusha
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006
Flip-flop with reduced retention voltage
SH Rasouli, A Datta, JM Shah, M Saint-Laurent, PK Parkar, S Bapat, ...
US Patent 9,673,786, 2017
Clock-gating cell with low area, low power, and low setup time
SH Rasouli, SJ Dillen, A Datta
US Patent 9,577,635, 2017
Clock-gated synchronizer
SH Rasouli, A Datta, O Kwon
US Patent App. 13/767,729, 2014
Low power and high performance clock delayed domino logic using saturated keeper
A Amirabadi, A Chehelcheraghi, SH Rasouli, A Seyedi, A Afzai-Kusha
2006 IEEE International Symposium on Circuits and Systems, 4 pp.-3176, 2006
Low power low leakage clock gated static pulsed flip-flop
AS Seyedi, SH Rasouli, A Amirabadi, A Afzali-Kusha
2006 IEEE International Symposium on Circuits and Systems, 4 pp.-3661, 2006
High frequency synchronizer
SH Rasouli, A Datta, S Marimuthu, O Kwon
US Patent 9,020,084, 2015
Semi-data gated flop with low clock power/low internal power with minimal area overhead
SH Rasouli, X Chen, V Boynapalli
US Patent 9,979,381, 2018
Effect of grain orientation on NBTI variation and recovery in emerging Metal-Gate Devices
SH Rasouli, K Banerjee
IEEE Electron Device Letters 31 (8), 794-796, 2010
Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications
A Abbasian, SH Rasouli, J Derakhshandeh, A Afzali-Kusha, M Nourani
Southwest Symposium on Mixed-Signal Design, 2003., 87-89, 2003
Clock gating cell for low setup time for high frequency designs
SH Rasouli, X Chen, V Boynapalli
US Patent App. 15/372,866, 2018
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