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Juan Pablo Duarte Sepulveda
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A polydimethylsiloxane (PDMS) sponge for the selective absorption of oil from water
SJ Choi, TH Kwon, H Im, DI Moon, DJ Baek, ML Seol, JP Duarte, YK Choi
ACS applied materials & interfaces 3 (12), 4552-4556, 2011
6012011
Sensitivity of threshold voltage to nanowire width variation in junctionless transistors
SJ Choi, DI Moon, S Kim, JP Duarte, YK Choi
IEEE Electron Device Letters 32 (2), 125-127, 2010
2932010
Negative capacitance in short-channel FinFETs externally connected to an epitaxial ferroelectric capacitor
AI Khan, K Chatterjee, JP Duarte, Z Lu, A Sachid, S Khandelwal, ...
IEEE Electron Device Letters 37 (1), 111-114, 2015
2172015
Simple analytical bulk current model for long-channel double-gate junctionless transistors
JP Duarte, SJ Choi, DI Moon, YK Choi
IEEE Electron Device Letters 32 (6), 704-706, 2011
1852011
FinFET modeling for IC simulation and design: using the BSIM-CMG standard
YS Chauhan, DD Lu, S Venugopalan, S Khandelwal, JP Duarte, ...
Academic Press, 2015
1772015
A full-range drain current model for double-gate junctionless transistors
JP Duarte, SJ Choi, YK Choi
IEEE transactions on electron devices 58 (12), 4219-4225, 2011
1572011
BSIM—SPICE models enable FinFET and UTB IC designs
N Paydavosi, S Venugopalan, YS Chauhan, JP Duarte, S Jandhyala, ...
IEEE Access 1, 201-215, 2013
1272013
Investigation of silicon nanowire gate-all-around junctionless transistors built on a bulk substrate
DI Moon, SJ Choi, JP Duarte, YK Choi
IEEE Transactions on Electron Devices 60 (4), 1355-1360, 2013
1142013
BSIM6: Analog and RF compact model for bulk MOSFET
YS Chauhan, S Venugopalan, MA Chalkiadaki, MAU Karim, H Agarwal, ...
IEEE Transactions on Electron Devices 61 (2), 234-244, 2013
1082013
A compact model of quantum electron density at the subthreshold region for double-gate junctionless transistors
JP Duarte, MS Kim, SJ Choi, YK Choi
IEEE Transactions on Electron Devices 59 (4), 1008-1012, 2012
892012
Compact models of negative-capacitance FinFETs: Lumped and distributed charge models
JP Duarte, S Khandelwal, AI Khan, A Sachid, YK Lin, HL Chang, ...
2016 IEEE International Electron Devices Meeting (IEDM), 30.5. 1-30.5. 4, 2016
882016
An underlap channel-embedded field-effect transistor for biosensor application in watery and dry environment
JY Kim, JH Ahn, SJ Choi, M Im, S Kim, JP Duarte, CH Kim, TJ Park, ...
IEEE Transactions on Nanotechnology 11 (2), 390-394, 2011
782011
Impact of parasitic capacitance and ferroelectric parameters on negative capacitance FinFET characteristics
S Khandelwal, JP Duarte, AI Khan, S Salahuddin, C Hu
IEEE Electron Device Letters 38 (1), 142-144, 2016
752016
Engineering negative differential resistance in NCFETs for analog applications
H Agarwal, P Kushwaha, JP Duarte, YK Lin, AB Sachid, MY Kao, ...
IEEE Transactions on Electron Devices 65 (5), 2033-2039, 2018
702018
A nonpiecewise model for long-channel junctionless cylindrical nanowire FETs
JP Duarte, SJ Choi, DI Moon, YK Choi
IEEE Electron Device Letters 33 (2), 155-157, 2011
692011
BSIM-CMG: Standard FinFET compact model for advanced circuit design
JP Duarte, S Khandelwal, A Medury, C Hu, P Kushwaha, H Agarwal, ...
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
562015
A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model
YKC JP Duarte, SJ Choi, DI Moon
IEEE TRANSACTIONS ON ELECTRON DEVICES 60 (2), 848-855, 2013
522013
Circuit performance analysis of negative capacitance FinFETs
S Khandelwal, AI Khan, JP Duarte, AB Sachid, S Salahuddin, C Hu
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
502016
A universal core model for multiple-gate field-effect transistors. Part I: Charge model
JP Duarte, SJ Choi, DI Moon, JH Ahn, JY Kim, S Kim, YK Choi
IEEE Transactions on Electron Devices 60 (2), 840-847, 2012
492012
Modeling of GaN-based normally-off FinFET
C Yadav, P Kushwaha, S Khandelwal, JP Duarte, YS Chauhan, C Hu
IEEE electron device letters 35 (6), 612-614, 2014
452014
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