| The rocket chip generator K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016 | 853* | 2016 |
| FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, N Pemberton, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 277 | 2018 |
| Chipyard: Integrated design, simulation, and implementation framework for custom socs A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ... IEEE Micro 40 (4), 10-21, 2020 | 215 | 2020 |
| FASED: FPGA-Accelerated Simulation and Evaluation of DRAM D Biancolin, S Karandikar, D Kim, J Koenig, A Waterman, J Bachrach, ... Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 40 | 2019 |
| Evaluation of RISC-V RTL with FPGA-accelerated simulation D Kim, C Celio, D Biancolin, J Bachrach, K Asanovic First Workshop on Computer Architecture Research with RISC-V, 2017 | 32 | 2017 |
| A hardware accelerator for computing an exact dot product J Koenig, D Biancolin, J Bachrach, K Asanovic 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH), 114-121, 2017 | 30 | 2017 |
| DESSERT: Debugging RTL effectively with state snapshotting for error replays across trillions of cycles D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanović 2018 28th International Conference on Field Programmable Logic and …, 2018 | 28 | 2018 |
| Golden Gate: Bridging the resource-efficiency gap between ASICs and FPGA prototypes A Magyar, D Biancolin, J Koenig, S Seshia, J Bachrach, K Asanović 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 27 | 2019 |
| Jitpcb J Bachrach, D Biancolin, A Buchan, DW Haldane, R Lin 2016 IEEE/RSJ International Conference on Intelligent Robots and Systems …, 2016 | 15 | 2016 |
| Fine-grained interconnect synthesis A Rodionov, D Biancolin, J Rose ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (4), 1-22, 2016 | 12 | 2016 |
| The Rocket Chip Generator: Tech. Rep. UCB/EECS-2016-17 K Asanović, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... EECS Department, University of California Berkeley, 2016 | 8 | 2016 |
| Accessible, FPGA resource-optimized simulation of multiclock systems in firesim D Biancolin, A Magyar, S Karandikar, A Amid, B Nikolić, J Bachrach, ... IEEE Micro 41 (4), 58-66, 2021 | 6 | 2021 |
| Debugging RISC-V processors with FPGA-accelerated RTL simulation in the FPGA cloud D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanovic Appears in the 2nd Workshop on Computer Architecture Research with RISC-V …, 2018 | 6 | 2018 |
| Chipyard-An integrated SoC research and implementation environment A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 4 | 2020 |
| Simulator independent coverage for RTL hardware languages K Laeufer, V Iyer, D Biancolin, J Bachrach, B Nikolić, K Sen Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 3 | 2023 |
| Automated, FPGA-Based Hardware Emulation of Dynamic Frequency Scaling DT Biancolin eScholarship, University of California, 2021 | 1 | 2021 |
| Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research S Karandikar, D Biancolin, A Amid, N Pemberton, A Ou, R Katz, B Nikolic, ... | 1 | 2019 |
| RETROSPECTIVE: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, N Pemberton, ... | | |
Krste AsanovicUC BerkeleyVerified email at berkeley.edu
