| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE International Electron Devices Meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 175 | 2016 |
| Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition K Cheng, FL LIE, ER Miller, S TEEHAN US Patent 10,083,962, 2018 | 109* | 2018 |
| Air gap spacer for metal gates MA Bergendahl, K Cheng, FL Lie, ER Miller, JR Sporre, S Teehan US Patent 9,608,065, 2017 | 79 | 2017 |
| Nanosheet channel-to-source and drain isolation MA Bergendahl, K Cheng, FL Lie, ER Miller, JR Sporre, S Teehan US Patent 9,620,590, 2017 | 78 | 2017 |
| Forming stacked nanowire semiconductor device MA Bergendahl, K Cheng, FL Lie, ER Miller, JC Shearer, JR Sporre, ... US Patent App. 15/008,615, 2017 | 77 | 2017 |
| Spacer formation preventing gate bending B Pranatharthiharan, ER Miller, SC Seo, JR Sporre US Patent 10,256,239, 2019 | 56* | 2019 |
| EUV patterning successes and frontiers N Felix, D Corliss, K Petrillo, N Saulnier, Y Xu, L Meli, H Tang, A De Silva, ... Extreme Ultraviolet (EUV) Lithography VII 9776, 97761O, 2016 | 39 | 2016 |
| Vertical transport field effect transistor with precise gate length definition MA Bergendahl, K Cheng, FL LIE, ER Miller, JR Sporre, S TEEHAN US Patent 10,269,931, 2019 | 34* | 2019 |
| Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices H Jagannathan, B Anderson, CW Sohn, G Tsutsui, J Strane, R Xie, S Fan, ... 2021 IEEE International Electron Devices Meeting (IEDM), 26.1. 1-26.1. 4, 2021 | 31 | 2021 |
| Air gap spacer for metal gates MA Bergendahl, K Cheng, FL LIE, ER Miller, JR Sporre, S TEEHAN US Patent 10,043,801, 2018 | 31* | 2018 |
| Vertical transport field effect transistor with precise gate length definition MA Bergendahl, K Cheng, FL Lie, ER Miller, JR Sporre, S Teehan US Patent App. 15/195,332, 2017 | 23 | 2017 |
| Method to form dual channel semiconductor material fins K Cheng, RO Jung, FL Lie, ER Miller, JR Sporre, S Teehan US Patent 9,362,179, 2016 | 23 | 2016 |
| Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors MA Bergendahl, K Cheng, ER Miller, JR Sporre, S Teehan US Patent 9,905,643, 2018 | 20 | 2018 |
| Nitride etching with hydrofluorocarbons III: Comparison of C4H9F and CH3F for low-k′ nitride spacer etch processes H Miyazoe, N Marchack, RL Bruce, Y Zhu, M Nakamura, E Miller, ... Journal of Vacuum Science & Technology B, Nanotechnology and …, 2018 | 17 | 2018 |
| Advanced in-line metrology strategy for self-aligned quadruple patterning R Chao, M Breton, B L'herron, B Mendoza, R Muthinti, F Nelson, ... Metrology, Inspection, and Process Control for Microlithography XXX 9778, 977813, 2016 | 14 | 2016 |
| Single spacer for complementary metal oxide semiconductor process flow MA Bergendahl, K Cheng, J Dechene, FL Lie, ER Miller, JC Shearer, ... US Patent 9,450,095, 2016 | 13 | 2016 |
| Margin for fin cut using self-aligned triple patterning G Karve, FL Lie, ER Miller, SA Sieg, JR Sporre, S Teehan US Patent 9,997,369, 2018 | 12 | 2018 |
| Measuring local CD uniformity in EUV vias with scatterometry and machine learning D Kong, D Schmidt, J Church, C Liu, M Breton, C Murray, E Miller, L Meli, ... Metrology, Inspection, and Process Control for Microlithography XXXIV 11325 …, 2020 | 11 | 2020 |
| Vertical transport field effect transistor with precise gate length definition MA Bergendahl, K Cheng, FL Lie, ER Miller, JR Sporre, S Teehan US Patent App. 15/622,769, 2017 | 10 | 2017 |
| Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT G Tsutsui, R Bao, K Lim, RR Robison, RA Vega, J Yang, Z Liu, M Wang, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.4. 1-17.4. 4, 2016 | 10 | 2016 |
