| Deposition on a nanowire using atomic layer deposition D Guo, Z Li, K Wang, Z Zhang, Y Zhu US Patent 8,900,935, 2014 | 257 | 2014 |
| Stress-enhancing selective epitaxial deposition of embedded source and drain regions D Guo, Y Liu, C Pei, Y Tan US Patent App. 13/798,467, 2014 | 244 | 2014 |
| A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ... 2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011 | 129 | 2011 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 108 | 2014 |
| 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL S Narasimha, P Chang, C Ortolland, D Fried, E Engbrecht, K Nummy, ... 2012 International Electron Devices Meeting, 3.3. 1-3.3. 4, 2012 | 103 | 2012 |
| Self-aligned contact combined with a replacement metal gate/high-K gate dielectric J Yuan, D Guo, KH Wong, Y Wang, G Wang US Patent 8,481,415, 2013 | 79 | 2013 |
| Channel geometry impact and narrow sheet effect of stacked nanosheet CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ... 2018 IEEE international electron devices meeting (IEDM), 28.6. 1-28.6. 4, 2018 | 77 | 2018 |
| Integration of SMT in replacement gate FINFET process flow M Cai, D Guo, CC Yeh US Patent 8,697,523, 2014 | 73 | 2014 |
| Challenges and opportunities for high performance 32 nm CMOS technology JW Sleight, I Lauer, O Dokumaci, DM Fried, D Guo, B Haran, S Narasimha, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 67 | 2006 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 65 | 2016 |
| Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019 | 64 | 2019 |
| Fin field effect transistor with variable channel thickness for threshold voltage tuning M Cai, D Guo, CH Lin, CC Yeh US Patent 8,513,131, 2013 | 56 | 2013 |
| Forming wrap-around silicide contact on finFET D Guo, H Jagannathan, Z Liu, S Mochizuki US Patent 9,318,581, 2016 | 55 | 2016 |
| FinFET structure having fully silicided fin A Bryant, H Bu, D Guo, WE Haensch, CC Yeh US Patent 8,753,964, 2014 | 45 | 2014 |
| Strained finFET with an electrically isolated channel HK Utomo, K Cheng, R Divakaruni, D Guo, MH Na, R Ramachandran, ... US Patent 8,928,086, 2015 | 42 | 2015 |
| Graphene sensor D Guo, SJ Han, CH Lin, N Su US Patent App. 12/727,434, 2011 | 42 | 2011 |
| Self-aligned carbon electronics with embedded gate electrode D Guo, SJ Han, KKH Wong, J Yuan US Patent 8,455,365, 2013 | 41 | 2013 |
| Replacement gate electrode with a tungsten diffusion barrier layer D Guo, SJ Han, KKH Wong, J Yuan US Patent App. 13/118,750, 2012 | 41 | 2012 |
| Parasitic resistance reduction strategies for advanced CMOS FinFETs beyond 7nm H Wu, O Gluschenkov, G Tsutsui, C Niu, K Brew, C Durfee, C Prindle, ... 2018 IEEE International Electron Devices Meeting (IEDM), 35.4. 1-35.4. 4, 2018 | 40 | 2018 |
| Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel S Mochizuki, M Bhuiyan, H Zhou, J Zhang, E Stuckert, J Li, K Zhao, ... 2020 IEEE International Electron Devices Meeting (IEDM), 2.3. 1-2.3. 4, 2020 | 34 | 2020 |
